ISL12021 Datasheet, PDF (9/24 Pages) Intersil Corporation – Real Time Clock with On Chip Temp Compensation ±5ppm

ISL12021
Oscillator Compensation
The ISL12021 provides both initial timing correction and
temperature correction due to variation of the crystal
oscillator. Analog and Digital trimming control is provided for
initial adjustment, and a temperature compensation function
is provided to automatically correct for temperature drift of
the crystal. Initial values for the temperature coefficient
(ALPHA) and crystal capacitance (BETA) are required for
best accuracy. The function can be enabled/disabled at any
time and can be used in battery mode as well.
Register Descriptions
The battery-backed registers are accessible following a
slave byte of “1101111x” and reads or writes to addresses
[00h:13h]. The defined addresses and default values are
described in the Table 1. The battery backed general
purpose SRAM has a different slave address (1010111x), so
it is not possible to read/write that section of memory while
accessing the registers.
REGISTER ACCESS
The contents of the registers can be modified by performing
a byte or a page write operation directly to any register
address.
The registers are divided into 8 sections. They are:
1. Real Time Clock (7 bytes): Address 00h to 06h.
2. Control and Status (9 bytes): Address 07h to 0Fh.
3. Alarm (6 bytes): Address 10h to 15h.
4. Time Stamp for Battery Status (5 bytes): Address 16h to
1Ah.
5. Time Stamp for VDD Status (5 bytes): Address 1Bh to
1Fh.
6. Day Light Saving Time (8 bytes): 20h to 27h.
7. TEMP (2 bytes): 28h to 29h
8. Scratch Pad (6 bytes): Address 2Ah to 2Fh.
Write capability is allowable into the RTC registers (00h to
06h) only when the WRTC bit (bit 6 of address 08h) is set to
“1”. A multi-byte read or write operation is limited to one
section per operation. Access to another section requires a
new operation. A read or write can begin at any address
within the section.
A register can be read by performing a random read at any
address at any time. This returns the contents of that register
location. Additional registers are read by performing a
sequential read. For the RTC and Alarm registers, the read
instruction latches all clock registers into a buffer, so an
update of the clock does not change the time being read. At
the end of a read, the master supplies a stop condition to
end the operation and free the bus. After a read, the address
remains at the previous address +1 so the user can execute
a current address read and continue reading the next
register.
It is not necessary to set the WRTC bit prior to writing into
the control and status, alarm, and user SRAM registers.
9
FN6451.0
March 30, 2007