ISL12021 Datasheet, PDF (21/24 Pages) Intersil Corporation – Real Time Clock with On Chip Temp Compensation ±5ppm

ISL12021
the ISL12021 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last bit of
the last Data Byte (See Figure 12).
The Data Bytes are from the memory location indicated by
an internal pointer. This pointers initial value is determined
by the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 13h, the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
TABLE 23. SUGGESTED SURFACE MOUNT CRYSTALS
MANUFACTURER
PART NUMBER
Citizen
CM200S
Epson
MC-405, MC-406
Raltron
RSM-200S
SaRonix
32S12
Ecliptek
ECPSM29T-32.768K
ECS
ECX-306
Fox
FSM-327
Application Section
Battery Backup Details
Note that any input signal conditioning circuitry that is added
in regular operation or battery backup should have minimum
supply current drain, or have the capability to be put in a low
power standby mode. Op Amps such as the EL8176 have
low normal supply current (50µA) and standby power drain
(3µA), so can be used in battery backup applications.
Oscillator Crystal Requirements
The ISL12021 uses a standard 32.768kHz crystal. Either
through hole or surface mount crystals can be used.
Table 23 lists some recommended surface mount crystals
and the parameters of each. This list is not exhaustive and
other surface mount devices can be used with the ISL12021
if their specifications are very similar to the devices listed.
The crystal should have a required parallel load capacitance
of 12.5pF and an equivalent series resistance of less than
50k. The crystal’s temperature range specification should
match the application. Many crystals are rated for -10°C to
+60°C (especially through hole and tuning fork types), so an
appropriate crystal should be selected if extended
temperature range is required.
Layout Considerations
The crystal input at X1 has a very high impedance, and
oscillator circuits operating at low frequencies such as
32.768kHz are known to pick up noise very easily if layout
precautions are not followed. Most instances of erratic
clocking or large accuracy errors can be traced to the
susceptibility of the oscillator circuit to interference from
adjacent high speed clock or data lines. Careful layout of the
RTC circuit will avoid noise pickup and insure accurate
clocking.
Figure 11 shows a suggested layout for the ISL12021 device
using a surface mount crystal. Two main precautions should
be followed:
• Do not run the serial bus lines or any high speed logic
lines in the vicinity of the crystal. These logic level lines
can induce noise in the oscillator circuit to cause
misclocking.
• Add a ground trace around the crystal with one end
terminated at the chip ground. This will provide termination
for emitted noise in the vicinity of the RTC device.
FIGURE 11. SUGGESTED LAYOUT FOR ISL12021 AND
CRYSTAL
SIGNALS
FROM THE
MASTER
S
T _{IDENTIFICATION}
A
BYTE WITH
R
R/W=0
T
ADDRESS
BYTE
S
T _{IDENTIFICATION}
A _{BYTE WITH}
R
R/W = 1
T
S
A
A
T
C
C
O
K
K
P
SIGNAL AT
SDA
11011110
A
SIGNALS FROM
C
THE SLAVE
K
11011111
A
A
C
C _{FIRST READ}
K
K _{DATA BYTE}
LAST READ
DATA BYTE
FIGURE 12. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)
21
FN6451.0
March 30, 2007