ISL12021 Datasheet, PDF (14/24 Pages) Intersil Corporation – Real Time Clock with On Chip Temp Compensation ±5ppm

ISL12021
BATTERY SWITCHOVER BIT (BSW)
This bit selects either standard mode or low power mode
battery switchover. In standard Mode (BSW = 0), the V_DD
switches over to battery at the low trip point, typically 2.2V. In
Low Power Mode (BSW = 1), V_DD switches over to battery at
the battery voltage (V_BAT). Low power mode uses less power
in battery backup for applications requiring longer backup
times.
BATTERY LEVEL MONITOR TRIP BITS (VB85TP <2:0>)
Three bits selects the first alarm (85% of Nominal VBAT) level
for the battery voltage monitor. There are total of 7 levels that
could be selected for the first alarm.Any of the of levels could be
selected as the first alarm with no reference as to nominal
Battery voltage level. See Table 8.
TABLE 8. VB85T ALARM LEVEL
VB85Tp2
VB85Tp1
VB85Tp0
BATTERY
ALARM TRIP
LEVEL
(V)
0
0
0
2.125
0
0
1
2.295
0
1
0
2.550
0
1
1
2.805
1
0
0
3.060
1
0
1
4.250
1
1
0
4.675
BATTERY LEVEL MONITOR TRIP BITS (VB75TP <2:0>)
Three bits selects the second alarm (75% of Nominal VBAT)
level for the battery voltage monitor. There are total of 7 levels
that could be selected for the second alarm. Any of the of levels
could be selected as the second alarm with no reference as to
nominal Battery voltage level. See Table 9.
TABLE 9. BATTERY LEVEL MONITOR TRIP BITS
(VB75TP <2:0>)
VB75Tp2
VB75Tp1
VB75Tp0
BATTERY
ALARM TRIP
LEVEL
(V)
0
0
0
1.875
0
0
1
2.025
0
1
0
2.250
0
1
1
2.475
1
0
0
2.700
1
0
1
3.750
1
1
0
4.125
Initial ATR and DTR setting Register (ITRO)
These bits are to be used to trim the initial error (at room
temperature) of the crystal. Both digital (DTR) and analog
(ATR) trimming methods are available. The digital trimming
uses clock pulse skipping and insertion for frequency
adjustment. Analog trimming uses load capacitance
adjustment to pull the oscillator frequency. A range of
+64ppm to -63ppm is possible with combined Digital and
Analog trimming.
AGING AND INITIAL TRIM DIGITAL TRIMMING BITS
(IDTR0) <2:0>
These bits allow ±32ppm initial trimming range for the crystal
frequency. This is meant to be a coarse adjustment if the
range needed is outside that of the IATR control. See
Table 10. The IDTR0 register should only be changed while
the TSE (Temp Sense Enable) bit is “0”.
TABLE 10. IDTR0 TRIMMING RANGE
IDTR01
IDTR00
TRIMMING RANGE
0
0
Default /Disabled
0
1
+32ppm
1
0
0ppm
1
1
-32ppm
AGING AND INITIAL ANALOG TRIMMING BITS
(IATR0)<6:0>
The analog trimming register allows +32ppm to -31ppm
adjustment in 1ppm/bit increments. This enables fine
frequency adjustment for trimming initial crystal accuracy
error or to correct for aging drift. The IATR0 register should
only be changed while the TSE (temp sense enable) bit is
“0”.
TABLE 11. INITIAL ATR AND DTR SETTING REGISTER
ADDR 7
6
5
4
3
2
1
0
0Bh IDTR01 IDTR00 IATR05 IATR04 IATR03 IATR02 IATR01 IATR00
TABLE 12. IATRO TRIMMING RANGE
TRIMMING
IATR05 IATR04 IATR03 IATR02 IATR01 IATR00 RANGE
0
0
0
0
0
0
+32
0
0
0
0
0
1
+31
0
0
0
0
1
0
+30
0
0
0
0
1
1
+29
0
0
0
1
0
0
+28
0
0
0
1
0
1
+27
0
0
0
1
1
0
+26
0
0
0
1
1
1
+25
0
0
1
0
0
0
+24
0
0
1
0
0
1
+23
0
0
1
0
1
0
+22
0
0
1
0
1
1
+21
14
FN6451.0
March 30, 2007