ICM7170 Datasheet, PDF (9/13 Pages) Intersil Corporation – Microprocessor-Compatible, Real-Time Clock

ICM7170
PERIODIC INT’ MASK BITS
INTERRUPT MASK
REGISTER ^{D7 D6 D5 D4 D3 D2 D1 D0}
NOT
USED
ALARM MASK BIT
PIN 12
INT
V_IG
INT
SOURCE
PIN 11
INTERRUPT STATUS
REGISTER ^{D7 D6 D5 D4 D3 D2 D1 D0}
PERIODIC INT’ FLAGS
RD OF ADD HEX 10 = >RESET
ALARM FLAG BIT
GLOBAL INTERRUPT FLAG BIT
FIGURE 5. INTERRUPT OUTPUT CIRCUIT
INTERRUPT
ENABLE
COMMAND
REGISTER
BIT D4
Interrupt Operation
The Interrupt Output N-channel MOSFET (Figure 4) is enabled
whenever both the Interrupt Enable bit (D4 of the Command
Register) and a mask bit (D0 - D6 of the Interrupt Mask
Register) are set. The transistor is turned ON when a flag bit is
set that corresponds to one of the set mask bits. This also sets
the Global Interrupt Flag Bit (D7 of the Interrupt Status
Register). It is turned OFF when the Interrupt Status Register is
read. An interrupt can occur in both the operational and
standby modes of operation.
Since system power is usually applied between V_DD and V_SS,
the user can connect the Interrupt Source (pin 11) to V_SS. This
allows the Interrupt Output to turn on only while system powers
applied and will not be pulled to V_SS during standby operation.
If interrupts are required only during standby operation, then
the interrupt source pin should be connected to the battery’s
negative side (V_BACKUP). In this configuration, for example, the
interrupt could be used to turn on power for a cold boot.
Power Down Detector
The ICM7170 contains an on-chip power down detector that
eliminates the need for external components to support the
battery-backup switchover function, as shown in Figure 6.
Whenever the voltage from the V_SS pin to the V_BACKUP pin is
less than approximately 1.0V (the V_TH of the N-channel
MOSFET), the data bus I/O buffers in the ICM7170 are
automatically disabled and the chip cannot be read or written
to. This prevents random data from the microprocessor being
written to the clock registers as the power supply is going down.
Actual switchover to battery operation occurs when the voltage
on the V_BACKUP pin is within ±50mV of V_SS. This switchover
uncertainty is due to the offset voltage of the CMOS
comparator that is used to sense the battery voltage. During
battery backup, device operation is limited to timekeeping and
interrupt generation only, thus achieving micro- power current
drain. If an external battery-backup switch-over circuit is being
used with the ICM7170, or if standby battery operation is not
required, the V_BACKUP pin should be pulled up to V_DD through
a 2K resistor.
Time Synchronization
Time synchronization is achieved through bit D3 of the
Command Register, which is used to enable or disable the
100Hz clock from the counters. A logic “1” allows the counters
to function and a logic “0” disables the counters. To accurately
set the time, a logic “0” should be written into D3 and then the
desired times entered into the appropriate counters. The clock
is then started at the proper time by writing a logic “1” into D3 of
the Command Register.
Latched Data
To prevent ambiguity while the processor is gathering data from
the registers, the ICM7170 incorporates data latches and a
transparent transition delay circuit.
By accessing the 100ths of seconds counter an internal
store signal is generated and data from all the counters is
transferred into a 36-bit latch. A transition delay circuit will
delay a 100Hz transition during a READ cycle. The data
stored by the latches is then available for further processing
until the 100ths of seconds counter is read again. If a RD
signal is wider than 0.01s, 100Hz counts will be ignored.
Control Lines
The RD, WR, and CS signals are active low inputs. Data is
placed on the bus from counters or registers when RD is a
logic “0”. Data is transferred to counters or registers when
WR is a logic “0”. RD and WR must be accompanied by a
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