ICM7170 Datasheet, PDF (8/13 Pages) Intersil Corporation – Microprocessor-Compatible, Real-Time Clock

ICM7170
Detailed Description
Oscillator
The ICM7170 has an onboard CMOS Pierce oscillator with
an internally regulated voltage supply for maximum
accuracy, stability, and low power consumption. It operates
at any of four popular crystal frequencies: 32.768kHz,
1.046576MHz, 2.097152MHz, and 4.194304MHz (Note 1).
The crystal should be designed for the parallel resonant
mode of oscillation. In addition to the crystal, 2 or 3 load
capacitors are required, depending on the circuit topology
used.
The oscillator output is divided down to 4000Hz by one of
four divider ratios, determined by the two frequency
selection bits in the Command Register (D0 and D1 at
address 11H). This 4000Hz is then divided down to 100Hz,
which is used as the clock for the counters.
Time and calendar information is provided by 8 consecutive,
programmable counters: 100ths of, seconds, minutes, hours,
day of week, date, month, and year. The data is in binary
format with 8 bits per digit. See Table 3 for address
information. Any unused bits are held to a logic “0” during a
read and ignored during a write operation.
NOTE:
1. 4.94304MHz is not available over military temperature range.
Alarm Compare RAM
On the chip are 51 bits of Alarm Compare RAM grouped into
words of different lengths. These are used to store the time,
ranging from 10ths of seconds to years, for comparison to
the real-time counters. Each counter has a corresponding
RAM word. In the Alarm Mode an interrupt is generated
when the current time is equal to the alarm time. The RAM
contents are compared to the counters on a word by word
basis. If a comparison to a particular counter is unnecessary,
then the appropriate ‘M’ bit in Compare RAM should be set
to logic “1”.
The ‘M’ bit, referring to Mask bit, causes a particular RAM
word to be masked off or ignored during a compare. Table 3
shows addresses and Mask bit information.
Periodic Interrupts
The interrupt output can be programmed for 6 periodic
signals: 100Hz, 10Hz, once per second, once per minute,
once per hour, or once per day. The 100Hz and 10Hz
interrupts have instantaneous errors of ±2.5% and ±0.15%
respectively. This is because non-integer divider circuitry is
used to generate these signals from the crystal frequency,
which is a power of 2. The time average of these errors over
a 1 second period, however, is zero. Consequently, the
100Hz or 10Hz interrupts are not suitable as an aid in tuning
the oscillator; the 1 second interrupt must be used instead.
See General Notes, Note 6.
The periodic interrupts can occur concurrently and in
addition to alarm interrupts. The periodic interrupts are
controlled by bits in the interrupt mask register, and are
enabled by setting the appropriate bit to a “1” as shown in
Table 4. Bits D1 through D6 in the mask register, in
conjunction with bits D1 through D6 of the status register,
control the generation of interrupts according to Figure 5.
The interrupt status register, when read, indicates the cause
of the interrupt and resets itself on the rising edge of the RD
signal. When any of the counters having a corresponding bit
in the status register increments, that bit is set to a “1”
regardless of whether the corresponding bit in the interrupt
mask register is set or not.
Consequently, when the status register is read it will always
indicate which counters have increments and if an alarm
compare occurred, since the last time it was read. This
requires some special software considerations. If a slow
interrupt is enabled (i.e. hourly or daily), the program must
always check the slowest interrupt that has been enabled
first, because all the other lower order bits in the status
register will be set to “1” as well.
Bit D7 is the global interrupt bit, and when set to a “1”,
indicates that the ICM7170 did indeed generate a hardware
interrupt. This is useful when other interrupting devices in
addition to the ICM7170 are attached to the system
microprocessor, and all devices must be polled to determine
which one generated the interrupt.
See General Notes, Note 6.
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