HCA10014 Datasheet, PDF (9/17 Pages) Intersil Corporation – 15MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output

HCA10014
+7.5V
R_s
3
1MΩ
2
7
+
-
4
8
1
47pF -7.5V
0.01µF
NOISE
6
VOLTAGE
OUTPUT
30.1kΩ
0.01
µF
BW (-3dB) = 200kHz
1kΩ
TOTAL NOISE VOLTAGE (REFERRED
TO INPUT) = 23µV (TYP)
FIGURE 13. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED
FOR WIDEBAND NOISE MEASUREMENTS
Typical Applications
Voltage Followers
Operational amplifiers with very high input resistances are
particularly suited to service as voltage followers. Figure 14
shows the circuit of a classical voltage follower, together with
pertinent waveforms in a split supply configuration.
A voltage follower, operated from a single supply, is shown in
Figure 15, together with related waveforms. This follower
circuit is linear over a wide dynamic range, as illustrated by
the reproduction of the output waveform in Figure 15A with
input signal ramping. The waveforms in Figure 15B show
that the follower does not lose its input to output phase
sense, even though the input is being swung 7.5V below
ground potential. This unique characteristic is an important
attribute in both operational amplifier and comparator
applications. Figure 15B also shows the manner in which the
CMOS output stage permits the output signal to swing down
to the negative supply rail potential (i.e., ground in the case
shown). The digital-to-analog converter (DAC) circuit,
described later, illustrates the practical use of the HCA10014
in a single supply voltage follower application.
9-Bit CMOS DAC
A typical circuit of a 9-bit Digital-to-Analog Converter (DAC)
is shown in Figure 16. This system combines the concepts of
multiple switch CMOS lCs, a low cost ladder network of
discrete metal oxide film resistors, a HCA10014 op amp
connected as a follower, and an inexpensive monolithic
regulator in a simple single power supply arrangement. An
additional feature of the DAC is that it is readily interfaced
with CMOS input logic, e.g., 10V logic levels are used in the
circuit of Figure 16.
The circuit uses an R/2R voltage ladder network, with the
output potential obtained directly by terminating the ladder
arms at either the positive or the negative power supply
terminal. Each CD4007A contains three “inverters”, each
“inverter” functioning as a single pole double throw switch to
terminate an arm of the R/2R network at either the positive
or negative power supply terminal. The resistor ladder is an
assembly of 1% tolerance metal oxide film resistors. The five
arms requiring the highest accuracy are assembled with
series and parallel combinations of 806,000Ω resistors from
the same manufacturing lot.
A single 15V supply provides a positive bus for the follower
amplifier and feeds the CA3085 voltage regulator. A
“scale-adjust” function is provided by the regulator output
control, set to a nominal 10V level in this system. The line
voltage regulation (approximately 0.2%) permits a 9-bit
accuracy to be maintained with variations of several volts in
the supply. The flexibility afforded by the CMOS building
blocks simplifies the design of DAC systems tailored to
particular needs.
Single Supply, Absolute Value, Ideal Full Wave
Rectifier
An absolute value circuit is shown in Figure 17. During
positive excursions, the input signal is fed through the
feedback network directly to the output. Simultaneously, the
positive excursion of the input signal also drives the output
terminal (No. 6) of the inverting amplifier in a negative going
excursion such that the 1N914 diode effectively disconnects
the amplifier from the signal path. During a negative going
excursion of the input signal, the HCA10014 functions as a
normal inverting amplifier with a gain equal to -R₂/R₁. When
the equality of the two equations shown in Figure 17 is
satisfied, the full wave output is symmetrical.
Peak Detectors
Peak detector circuits are easily implemented, as illustrated
in Figure 18 for both the peak positive and the peak negative
circuit. It should be noted that with large signal inputs, the
bandwidth of the peak negative circuit is much less than that
of the peak positive circuit. The second stage of the
HCA10014 limits the bandwidth in this case. Negative going
output signal excursion requires a positive going signal
excursion at the collector of transistor Q₁₁, which is loaded
by the intrinsic capacitance of the associated circuitry in this
mode. On the other hand, during a negative going signal
excursion at the collector of Q₁₁, the transistor functions in
an active “pull down” mode so that the intrinsic capacitance
can be discharged more expeditiously.
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