HCA10014 Datasheet, PDF (6/17 Pages) Intersil Corporation – 15MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output

HCA10014
through D₈ provide gate oxide protection against high
voltage transients, including static electricity during handling
for Q₆ and Q₇.
HCA10014
V+
7
200µA 1.35mA 200µA 8mA
BIAS CKT.
(NOTE 5)
0mA
(NOTE 6)
+
3
INPUT
2
-
A_V ≈ 5X
A_V ≈
6000X
A_V ≈
30X
OUTPUT
6
V-
4
51
C_C
8
OFFSET
NULL
COMPENSATION
(WHEN REQUIRED)
STROBE
NOTES:
5. Total supply voltage (for indicated voltage gains) = 15V with input
terminals biased so that Terminal 6 potential is +7.5V above
Terminal 4.
6. Total supply voltage (for indicated voltage gains) = 15V with
output terminal driven to either supply rail.
FIGURE 7. BLOCK DIAGRAM OF THE HCA10014
Second Stage
Most of the voltage gain is provided by the second amplifier
stage, consisting of bipolar transistor Q₁₁ and its cascade
connected load resistance provided by PMOS transistors Q₃
and Q₅. The source of bias potentials for these PMOS
transistors is subsequently described. Miller Effect
compensation (roll off) is accomplished by simply connecting
a small capacitor between Terminals 1 and 8. A 47pF
capacitor provides sufficient compensation for stable unity
gain operation in most applications.
Bias Source Circuit
At total supply voltages, somewhat above 8.3V, resistor R₂
and zener diode Z₁ serve to establish a voltage of 8.3V
across the series connected circuit, consisting of resistor R₁,
diodes D₁ through D₄, and PMOS transistor Q₁. A tap at the
junction of resistor R₁ and diode D₄ provides a gate bias
potential of about 4.5V for PMOS transistors Q₄ and Q₅ with
respect to Terminal 7. A potential of about 2.2V is developed
across diode connected PMOS transistor Q₁ with respect to
Terminal 7 to provide gate bias for PMOS transistors Q₂ and
Q₃. It should be noted that Q₁ is “mirror connected (see
Note 7)” to both Q₂ and Q₃. Since transistors Q₁, Q₂, Q₃ are
designed to be identical, the approximately 200µA current in
Q₁ establishes a similar current in Q₂ and Q₃ as constant
current sources for both the first and second amplifier
stages, respectively.
At total supply voltages somewhat less than 8.3V, zener
diode Z₁ becomes nonconductive and the potential,
developed across series connected R₁, D₁-D₄, and Q₁,
varies directly with variations in supply voltage.
Consequently, the gate bias for Q₄, Q₅ and Q₂, Q₃ varies in
accordance with supply voltage variations. This variation
results in deterioration of the power supply rejection ratio
(PSRR) at total supply voltages below 8.3V. Operation at
total supply voltages below about 4.5V results in seriously
degraded performance.
Output Stage
The output stage consists of a drain loaded inverting
amplifier using CMOS transistors operating in the Class A
mode. When operating into very high resistance loads, the
output can be swung within millivolts of either supply rail.
Because the output stage is a drain loaded amplifier, its gain
is dependent upon the load impedance. The transfer
characteristics of the output stage for a load returned to the
negative supply rail are shown in Figure 8. Typical op amp
loads are readily driven by the output stage. Because large
signal excursions are nonlinear, requiring feedback for good
waveform reproduction, transient delays may be
encountered. As a voltage follower, the amplifier can achieve
0.01% accuracy levels, including the negative supply rail.
NOTE:
7. For general information on the characteristics of CMOS transistor
pairs in linear circuit applications, see Document # 619, data
sheet on CA3600E “CMOS Transistor Array”.
17.5
SUPPLY VOLTAGE: V+ = 15, V- = 0V
15 ^{TA = 25oC}
LOAD RESISTANCE = 5kΩ
12.5
2kΩ
1kΩ
10 _500Ω
7.5
5
2.5
0
0 2.5
5 7.5 10 12.5 15 17.5 20 22.5
GATE VOLTAGE (TERMINALS 4 AND 8) (V)
FIGURE 8. VOLTAGE TRANSFER CHARACTERISTICS OF
CMOS OUTPUT STAGE
Input Current Variation with Common Mode Input
Voltage
As shown in the Table of Electrical Specifications, the input
current for the HCA10014 is typically 5pA at T_A = 25^oC when
Terminals 2 and 3 are at a common mode potential of +7.5V
with respect to negative supply Terminal 4. Figure 9 contains
data showing the variation of input current as a function of
6