HCA10014 Datasheet, PDF (5/17 Pages) Intersil Corporation – 15MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output

HCA10014
Schematic Diagram
BIAS CIRCUIT
CURRENT SOURCE FOR
Q₆ AND Q₇
Q₁
D₁
Z₁
D₂
8.3V
D₃
R₁
D₄
40kΩ _R2
5kΩ
Q₂
Q₄
NON-INV.
INPUT
3+
INV.-INPUT
2
-
INPUT STAGE
D₅ D₆
(NOTE 4) ^D7 ^D8
Q₆
Q₇
R₃
R₄
1kΩ
1kΩ
Q₉ Q₁₀
R₅
R₆
1kΩ
1kΩ
“CURRENT SOURCE
LOAD” FOR Q₁₁
Q₃
Q₅
SECOND
STAGE
Q₁₁
OUTPUT
STAGE
7 ^V+
Q₈
OUTPUT
6
Q₁₂
5
OFFSET NULL
1
COMPENSATION
NOTE:
4. Diodes D₅ through D₈ provide gate-oxide protection for MOSFET input stage.
8
STROBING
4 V-
Application Information
Circuit Description
Figure 7 is a block diagram of the HCA10014. The input
terminals may be operated down to 0.5V below the negative
supply rail, and the output can be swung very close to either
supply rail in many applications. Consequently, the
HCA10014 is ideal for single supply operation. Three
Class A amplifier stages, having the individual gain
capability and current consumption shown in Figure 7,
provide the total gain of the HCA10014. A biasing circuit
provides two potentials for common use in the first and
second stages. Terminal 8 can be used both for phase
compensation and to strobe the output stage into
quiescence. When Terminal 8 is tied to the negative supply
rail (Terminal 4) by mechanical or electrical means, the
output potential at Terminal 6 essentially rises to the positive
supply rail potential at Terminal 7. This condition of
essentially zero current drain in the output stage under the
strobed “OFF” condition can only be achieved when the
ohmic load resistance presented to the amplifier is very high
(e.g., when the amplifier output is used to drive CMOS digital
circuits in Comparator applications).
Input Stage
The circuit is shown in the schematic diagram. It consists of
a differential input stage using PMOS field effect transistors
(Q₆, Q₇) working into a mirror pair of bipolar transistors (Q₉,
Q₁₀) functioning as load resistors together with resistors R₃
through R₆. The mirror pair transistors also function as a
differential to single ended converter to provide base drive to
the second stage bipolar transistor (Q₁₁). Offset nulling,
when desired, can be effected by connecting a 100,000Ω
potentiometer across Terminals 1 and 5 and the
potentiometer slider arm to Terminal 4. Cascade connected
PMOS transistors Q₂, Q₄ are the constant current source for
the input stage. The biasing circuit for the constant current
source is subsequently described. The small diodes D₅
5