CD4508BMS Datasheet, PDF (9/9 Pages) Intersil Corporation – CMOS Dual 4-Bit Latch

CD4508BMS
Bus Registers
RESET
CLOCK
SERIAL
DATA
STROBE
DISABLE
DISABLE
4-LINE
DATA
BUS
4 BIT SHIFT
REGISTER
4 BIT SHIFT
REGISTER
CD4015BMS
QUAD LATCH
(3 STATE)
QUAD LATCH
(3 STATE)
CD4508BMS
CD4508BMS
3-STATE
4 BIT LATCH
3-STATE
4 BIT LATCH
CD4508BMS
DATA BUS
4-LINE
DATA BUS
4-LINE
DATA BUS
CD4019BMS
3-STATE
3-STATE
A
4 BIT LATCH
4 BIT LATCH
B
FUNCTON SELECT
A
B
FUNCTION
0
0 Inhibit (All 0)
1
0 Select A Bus
0
1 Select B Bus
1
1 AI + BI
FIGURE 11. BUS REGISTER
FIGURE 12. DUAL MULTIPLEXED BUS REGISTER WITH FUNC-
TION SELECT
Chip Dimensions and Pad Layouts
0
94
90
10 20 30 40 50 60 70 80 90 96
80
70
60
50
91-99
(2.311-2.515)
40
30
20
10
0
4-10
(0.102-0.254)
93-101
(2.362-2.565)
Dimensions in parentheses are in milimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10^-3 inch.)
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-1156