CD4508BMS Datasheet, PDF (1/9 Pages) Intersil Corporation – CMOS Dual 4-Bit Latch

CD4508BMS
December 1992
CMOS Dual 4-Bit Latch
Features
Pinout
• High-Voltage Types (20-Volt Rating)
• Two Independent 4-Bit Latches
CD4508BMS
TOP VIEW
• Individual Master Reset for Each 4-Bit Latch
• 3-State Outputs with High-Impedance State for Bus
Line Applications
• Medium-Speed Operation: tPHL = tPLH = 70nS (Typ.)
at VDD = 10V and CL = 50pF
• 100% Tested for Quiescent Current at 20V
• 5V, 10V, and 15V Parametric Ratings
• Standardized, Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and 25^oC
• Noise Margin (Full Package-Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets all Requirements of JEDEC Tentative Standard
No. 13B, "Standard Specifications for Description of
‘B’ Series CMOS Devices"
Applications
• Buffer Storage
• Holding Registers
• Data Storage and Multiplexing
Description
CD4508BMS dual 4-bit latch contains two identical 4-bit
latches with separate STROBE, RESET, and OUTPUT
DISABLE controls. With the STROBE line in the high state,
the data on the "D" inputs appear at the corresponding "Q"
outputs provided the DISABLE line is in the low state.
Changing the STROBE line to the low state locks the data
into the latch. A high on the reset line forces the outputs to a
low level regardless of the state of the STROBE input. The
outputs are forced to the high-impedance state for bus line
applications by a high level on the DISABLE input.
RESET A ¹
STROBE A ²
OUTPUT DISABLE A ³
D0A ⁴
Q0A ⁵
D1A ⁶
Q1A ⁷
D2A ⁸
Q2A 9
D3A 10
Q3A 11
VSS 12
Functional Diagram
OUTPUT
DISABLE
D0A
D1A
D2A
D3A
STROBE
RESET
OUTPUT
DISABLE
D0B
D1B
D2B
D3B
STROBE
RESET
4-BIT
LATCH
4-BIT
LATCH
24 VDD
23 Q3B
22 D3B
21 Q2B
20 D2B
19 Q1B
18 D1B
17 Q0B
16 D0B
15 OUTPUT DISABLE B
14 STROBE B
13 RESET B
3-STATE
OUTUTS
Q0A
Q1A
Q2A
Q3A
3-STATE
OUTUTS
Q0B
Q1B
Q2B
Q3B
The CD4508BMS is supplied in these 24 lead outline
packages:
Braze Seal DIP H4V
Frit Seal DIP
H1Z
Ceramic Flatpack H4P
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1148
File Number 3337