CD4508BMS Datasheet, PDF (6/9 Pages) Intersil Corporation – CMOS Dual 4-Bit Latch

Specifications CD4508BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
Static Burn-In 1 5, 7, 9, 11, 17, 19,
Note 1
21, 23
GROUND
1-4, 6, 8, 10,
12-16, 18, 20, 22
VDD
24
9V ± -0.5V
50kHz
25kHz
Static Burn-In 2 5, 7, 9, 11, 17, 19,
12
1-4, 6, 8, 10, 13-
Note 1
21, 23
16, 18, 20, 22, 24
Dynamic Burn-
-
In Note 1
1, 3, 12, 13, 15
2, 14, 24
5, 7, 9, 11, 17, 19, 4, 6, 8, 10, 16, 18,
-
21, 23
20, 22
Irradiation
5, 7, 9, 11, 17, 19,
12
1-4, 6, 8, 10, 13-
Note 2
21, 23
16, 18, 20, 22, 24
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
Logic Diagram
OUTPUT DISABLE
*
3
OUTPUT
DISABLE - A
OUTPUT DISABLE
*
1
RESET - A
ST
*
4(6, 8, 10)
p
Dn - A
n
ST
ST ^ST
p
*
2
n
ST
STROBE - A
ST
* All inputs protected by CMOS protection network.
TYPICAL LATCH
VDD
VSS
Qn-A
5(7, 9, 11)
OUTPUT
VDD
VSS
FIGURE 1. LOGIC DIAGRAM (A-SECTION), 1 OF 4 IDENTICAL LATCHES
WITH COMMON OUTPUT DISABLE, RESET AND STROBE
TRUTH TABLE
RESET DISABLE STROBE D INPUT
0
0
1
1
0
0
1
0
0
0
0
X
1
0
X
X
X
1
X
X
1 = HIGH LEVEL
0 = LOW LEVEL
X = DON’T CARE
Z = HIGH IMPEDANCE
Q OUTPUT
1
0
LATCHED
0
Z
7-1153