CD4035BMS Datasheet, PDF (9/10 Pages) Intersil Corporation – CMOS 4 -Stage Parallel In/Parallel Out Shift Register

CD4035BMS
VDD
9
10
11
12
7
PI-1 PI-2 PI-3 PI-4
P/S
2
T/C
6
CL
4
4 STAGE REGISTER
J
3
K
5
R Q1
Q2
Q3
Q4
1
15
14
13
2345
1/2
CD4012
1
2345
CD4002
1/2
1
“E” CONTROL
9,10 11,12
CD4002
1/2
13
9,10 11,12
1/2
CD4012
13
1
5
1/2
4 _CD4030
6
1
2
1/2
CD4030
3
FIGURE 11(a). DOUBLE SEQUENCE GENERATOR
Control = E = 0
1
Q1 Q2 Q3 Q4
ABCD
Q1 Q2 Q3 Q4
ABCD
0 0 0 0 0 15 1 1 1 1
1 1 0 0 0 14 0 1 1 1
2 0 1 0 0 13 1 0 1 1
5 1 0 1 0 10 0 1 0 1
10 0 1 0 1 5 1 0 1 0
4 0 0 1 0 11 1 1 0 1
9100160110
3 1 1 0 0 12 0 0 1 1
6011091001
13 1 0 1 1 2 0 1 0 0
11 1 1 0 1 4 0 0 1 0
7111080001
14 0 1 1 1 1 1 0 0 0
12 0 0 1 1 3 1 1 0 0
8000171110
Using a control line (E) two different state sequences can
be generated. For example, suppose the following two
sequences are desired on command (control line E).
FIGURE 11(b). STATE SEQUENCES
CLOCK
CARRY
INPUT
VDD
RESET
TO
UNITS
REGISTER
9
10
11
12
7
PI-1 PI-2 PI-3 PI-4
P/S
6
CL
4
J
3
UNITS REGISTER
K
2
T/C
5
R Q1
Q2
Q3
Q4
1
15
14
13
BCD
UNITS
OUT
9
10
11
12
7
PI-1 PI-2 PI-3 PI-4
P/S
6
CL
4
J
3
TENS REGISTER
K
2
VDD
T/C
5
R Q1
Q2
Q3
Q4
1
15
14
13
BCD
TENS
OUT
P/S
FIG 7
BCD UNITS
(BIDEC LOGIC)
PI-2
PI-3
PI-4
CARRY
FORWARD
TO
TENS
REGISTER
P/S
FIG 7
BCD TENS
(BIDEC LOGIC)
PI-2
PI-3
PI-4
CARRY
FORWARD
TO
NEXT
DECADE
FIGURE 12. BINARY-TO-BCD CONVERTER
7-859