CD4035BMS Datasheet, PDF (1/10 Pages) Intersil Corporation – CMOS 4 -Stage Parallel In/Parallel Out Shift Register

CD4035BMS
December 1992
CMOS 4 -Stage Parallel
In/Parallel Out Shift Register
Features
Description
• J - K Serial Inputs and True/Complement Outputs
• High Voltage Type (20V Rating)
• 4-Stage Clocked Shift Operation
• Synchronous Parallel Entry on All 4 Stages
• JK Inputs on First Stage
• Asynchronous True/Complement Control on All Out-
puts
• Static Flip-Flop Operation; Master-Slave Configura-
tion
• Buffered Inputs and Outputs
• High Speed Operation 12MHz (Typ) at VDD = 10V
• 100% Tested for Quiescent Current at 20V
• Standardized, Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
Number 13A, “Standard Specifications for Description
of ‘B’ Series CMOS Devices”
Applications
• Counters, Registers
- Arithmetic-Unit Registers
- Shift Left/Shift Right Registers
- Serial-to-Parallel/Parallel-to-Serial Conversions
• Sequence Generation
• Control Circuits
• Code Conversion
CD4035BMS is a four stage clocked signal serial register
with provision for synchronous PARALLEL inputs to each
stage and SERIAL inputs to the first stage via JK logic. Reg-
ister stages 2, 3, and 4 are coupled in a serial D flip-flop con-
figuration when the register is in the serial mode
(PARALLEL/SERIAL control low).
Parallel entry into each register stage is permitted when the
PARALLEL/SERIAL control is high.
In the parallel or serial mode information is transferred on
positive clock transitions.
When the TRUE/COMPLEMENT control is high, the true
contents of the register are available at the output terminals.
When the TRUE/COMPLEMENT control is low, the outputs
are the complements of the data in the register. The TRUE/
COMPLEMENT control functions asynchronously with
respect to the CLOCK signal.
JK input logic is provided on the first stage SERIAL input to
minimize logic requirements particularly in counting and
sequence-generation applications. With JK inputs connected
together, the first stage becomes a D flip-flop. An asynchro-
nous common, RESET is also provided.
The CD4035BMS series type is supplied in these 16 lead
outline packages
Braze Seal DIP H4T
Frit Seal DIP
H1F
Ceramic Flatpack H6W
Pinout
CD4035BMS
TOP VIEW
Q1/Q1 1
TRUE/
COMP.
2
K3
J4
RESET 5
CLOCK 6
P/S 7
VSS 8
16 VDD
15 Q2/Q2
14 Q3/Q3
13 Q4/Q4
12 PI-4
11 PI-3
10 PI-2
9 PI-1
Functional Diagram
4
SER
J
3
IN K
6
CLK
7
P/S
2
T/C
5
RESET
VDD = 16
VSS = 8
PARALLEL IN
1
2
3
4
9
10
11
12
4-STAGE REGISTER
1
15
14
13
Q1/Q1 Q2/Q2 Q3/Q3 Q4/Q4
T/C OUT
FIRST STAGE TRUTH TABLE
tn-1 (INPUT)
tn
(OUTPUT)
CL
J K R Qn-1
Qn
0X0 0
0
1X0 0
1
X00 1
0
1 0 0 Qn-1 Qn-1
Toggle
Mode
X10 1
1
X X 0 Qn-1 Qn-1
X
XX1 X
0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-851
File Number 3308