CD4035BMS Datasheet, PDF (6/10 Pages) Intersil Corporation – CMOS 4 -Stage Parallel In/Parallel Out Shift Register

Specifications CD4035BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
Logic Diagram
*
4
J
*
3
K
*
5
RESET
*
6
CLOCK
*
7
PARALLEL/
SERIAL CONTROL
*
2
T
p
T
n
T
T
*
9
P
DQ
R
CL Q
PS
T
p
n
T
*
*
10
11
P
DQ
R
CL Q
PS
P
DQ
R
CL Q
PS
T
T
T
p
p
p
n
n
n
T
T
T
TRUE/COMPLEMENT
P/S = 0 = SERIAL MODE
T/C = 1= TRUE OUTPUTS
PS
P
DQ
P
p
n
R
≡ _PS
p
D
CL Q
n
PS
PS
PS
CL
p
n
CL
CL
1
Q1/Q1
CL
p
n
CL
PS
PS CL
CL
15
Q2/Q2
CL
Q
p
n
CL
CL
p
R
n
CL
*
12
*ALL INPUTS PROTECTED
BY CMOS INPUT
PROTECTION NETWORK
VDD
P
DQ
R
CL Q
PS
VSS
T
T
T
p
p
p
n
n
n
T
T
T
14
Q3/Q3
13
Q4/Q4
Q
FIGURE 1. TYPICAL STAGE DETAIL LOGIC
7-856