CD4035BMS Datasheet, PDF (8/10 Pages) Intersil Corporation – CMOS 4 -Stage Parallel In/Parallel Out Shift Register

CD4035BMS
Typical Performance Characteristics (Continued)
20
AMBIENT TEMPERATURE (T_A) = +25^oC
LOAD CAPACITANCE (CL) = 50PF
15
10
5
0
0
5
10
15
20
SUPPLY VOLTAGE (VDD) (V)
FIGURE 7. TYPICAL MAXIMUM CLOCK INPUT FREQUENCY
AS A FUNCTION OF SUPPLY VOLTAGE
10⁶
8
6
4
AMBIENT TEMPERATURE (T_A) = +25^oC
2
10⁵
8
6
4
SUPPLY VOLTAGE (VDD) = 15V
2
10⁴
8
6
4
2
10³
8
6
4
10V
10V
5V
CL = 50pF
2
CL = 15pF
10²
2 4 68 2 4 68 2 4 68 2 4 68 2 4 68
1
10
10²
10³
10⁴
INPUT FREQUENCY (fI) (kHz)
FIGURE 8. TYPICAL DYNAMIC POWER DISSIPATION AS A
FUNCTION OF CLOCK INPUT FREQUENCY
LEFT/RIGHT
RIGHT
SHIFT
INPUT
CLK
T/C
RESET
LEFT
SHIFT
OUTPUT
9
7
PI-1
P/S
4
J
3
K
6
CL
2
T/C
5
R Q1
10
PI-2
Q2
11
PI-3
Q3
12
PI-4
Q4
1
15
14
13
TRUE/COMP CONTROL IN TRUE MODE
LEFT
SHIFT
INPUT
RIGHT
SHIFT
OUTPUT
Q1 Q2 Q3 Q4
VDD
FIGURE 9. SHIFT LEFT/SHIFT RIGHT REGISTER
P/S
CARRY
FORWARD
PI-2
PI-3
PI-4
Using Couleur’s Technique (BIDEC)*, a binary number (most
significant bit, MSB) first is shifted and processed, such that
the BCD equivalent is obtained when the last binary bit is
clocked into the register. The CD4035BMS, with the correct
conversion logic, can also be used as a BCD-to-binary con-
verter.
*NOTE: The basic rule is: If a 4 or less is in a decade, shift with the
next clock pulse; if a 5 or greater is in a decade, add 3 and
then shift at the next clock pulse. For more information
refer to “IRE TRANSACTIONS ON ELECTRONIC COM-
PUTERS”, Dec. 1958, pages 313-316.
FIGURE 10. BIDEC LOGIC
7-858