CD40105BMS Datasheet, PDF (9/10 Pages) Intersil Corporation – CMOS FIFO Register

CD40105BMS
D0 ₄
D1 ₅
D2 6
D3 7
INPUT
BUFFERS
OUTPUT
BUFFERS
4 x 16
DATA
REGISTER
13 ^Q0
12 ^Q1
11 Q2
10 Q3
DATA-IN
READY (DIR)
2
3
SHIFT IN (SI)
CONTROL LOGIC
MASTER
9 _{RESET (MR)}
1
3-STATE
CONTROL
14
DATA-OUT
READY (DOR)
15
SHIFT OUT (SO)
SI
DOR
D0
Q0
D1
Q1
D2
Q2
D3
Q3
DIR MR SO
SI
DOR
D0
Q0
D1
Q1
D2
Q2
D3
Q3
DIR MR SO
FIGURE 8. CD40105BMS FUNCTIONAL BLOCK DIAGRAM
FIGURE 9. EXPANSION, 4-BITS WIDE-BY-16 N-BITS LONG
INPUTS
MASTER
RESET
SHIFT IN
(DATA VALID)
SHIFT OUT
OUTPUTS
INPUT READY
(CLEAR OUT)
OUTPUT READY
(CLEAR OUT)
≈ 2µs*
SHIFT-OUT PULSES
HAVE NO EFFECT
SHIFT-IN PULSES
HAVE NO EFFECT
≈ 2µs**
INPUTS
DATA IN (Dn)
3-STATE
(OUTPUT
ENABLE)
DATA OUT***
1 0 11 10 0 1 1 0 10 1 0 1 0
(UNKNOWN)
*AT VDD =5V - RIPPLE TIME FROM POSITION 1 TO POSITION 16
1
**AT VDD = 5V - RIPPLE TIME FROM POSITION 16 TO POSITION 1
***DATA VALID goes to high level in advance of the DATA OUT
by maximum of 50ns at VDD = 5V, 25ns at VDD = 10V,
and 20ns at VDD = 15V for CL = 50pF and T_A = 25^oC
0 11
10
FIGURE 10. TIMING DIAGRAM FOR THE CD40105BMS
HIGH
Z
INVALID
7-1325