CD40105BMS Datasheet, PDF (2/10 Pages) Intersil Corporation – CMOS FIFO Register

CD40105BMS
Unloading Data - As soon as the first word has rippled to
the output, DATA-OUT READY (DOR) goes high, and data
can be removed by a falling edge on the SO input. This fall-
ing edge causes the DOR signal to go low while the word on
the output is dumped and the next word moves to the output.
As long as valid data are available in the FIFO, the DOR sig-
nal will go high again signifying that the next word is ready at
the output. When the FIFO is empty, DOR will remain low,
and any further commands will be ignored until a “1” marker
ripples down to the last control register, when DOR goes
high. Unloading of data is inhibited while the 3-state control
input is high. The 3-state control signal should not be shifted
from high to low (data outputs turned on) while the SHIFT-
OUT is at logic 0. This level change would cause the first
word to be shifted out (unloaded) immediately and the data
to be lost.
Cascading - The CD40105BMS can be cascaded to form
longer registers simply by connecting the DIR to SO and
DOR to SI. In the cascaded mode, a MASTER RESET pulse
must be applied after the supply voltage is turned on. For
words wider than 4 bits, the DIR and the DOR outputs must
be gated together with AND gates. Their outputs drive the SI
and SO inputs in parallel, if expanding is done in both direc-
tions (see Figures 9 and 11).
3-State Outputs - In order to facilitate data busing, 3-state
outputs are provided on the data output lines, while the load
condition of the register can be detected by the state of the
DOR output.
Master Reset - A high on the MASTER RESET (MR) sets all
the control logic marker bits to “0”. DOR goes low and DIR
goes high. The contents of the data register are not
changed, only declared invalid, and will be superseded when
the first word is loaded. The shift-in must be low during Mas-
ter Reset.
The CD40105BMS is supplied in these 16-lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4X
H1F
H6W
Logic Diagram
MASTER
RESET
*⁹
SHIFT
IN
*³
R
SQ
RQ
1
SQ
2 DATA IN READY
(DIR)
RQ
2
SQ
4 - 15
SHIFT^* ₁₅
OUT
*
1 _{3 - STATE}
CONTROL
(OUTPUT
ENABLE)
RQ
16
SQ
DATA
READY
14
(DOR)
R
SQ
*_{D0 4}
*_{D1 5}
*_{D2 6}
*_{D3 7}
CL CL
4
LATCHES
POS 1
*ALL INPUTS PROTECTED BY
COS/MOS PROTECTION
NETWORK
CL CL
4
LATCHES
VDD
POS 2
CL CL
4
LATCHES
POS 3
VSS
7-1318
CL CL
4
LATCHES
POS 16
3
STATE
OUTPUT
BUFFERS
13 Q0
12 Q1
11 Q2
10 Q3
CL
DETAIL OF LATCHES
p
n
CL
CL
p
n
CL