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CD40105BMS Datasheet, PDF (1/10 Pages) Intersil Corporation – CMOS FIFO Register | |||
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CD40105BMS
December 1992
CMOS FIFO Register
Features
Description
⢠4 Bits x 16 Words
⢠High Voltage Type (20V Rating)
⢠Independent Asynchronous Inputs and Outputs
⢠3-State Outputs
⢠Expandable in Either Direction
⢠Status Indicators on Input and Output
⢠Reset Capability
⢠Standardized Symmetrical Output Characteristics
⢠100% Tested for Quiescent Current at 20V
⢠5V, 10V and 15V Parametric Ratings
⢠Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
⢠Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
⢠Meets All Requirements of JEDEC Tentative Standard
No. 13B, âStandard Speciï¬cations for Description of
âBâ Series CMOS Devicesâ
Applications
⢠Bit Rate Smoothing
⢠CPU/Terminal Buffering
⢠Data Communications
⢠Peripheral Buffering
⢠Line Printer Input Buffers
⢠Auto Dialers
⢠CRT Buffer Memories
⢠Radar Data Acquisition
CD40105BMS is a low-power ï¬rst-in-ï¬rst-out (FIFO) âelasticâ
storage register that can store 16 4-bit words. It is capable of
handling input and output data at different shifting rates. This
feature makes it particularly useful as a buffer between asyn-
chronous systems.
Each word position in the register is clocked by a control ï¬ip-
ï¬op, which stores a marker bit. A â1â signiï¬es that the posi-
tionâs data is ï¬lled and a â0â denotes a vacancy in that posi-
tion. The control ï¬ip-ï¬op detects the state of the preceding
ï¬ip-ï¬op and communicates its own status to the succeeding
ï¬ip-ï¬op. When a control ï¬ip-ï¬op is in the â0â state and sees a
â1â in the preceding ï¬ip-ï¬op, it generates a clock pulse that
transfers data from the preceding four data latches into its
own four data latches and resets the preceding ï¬ip-ï¬op to
â0â. The ï¬rst and last control ï¬ip-ï¬ops have buffered outputs.
Since all empty locations âbubbleâ automatically to the input
end, and all valid data ripple through to the output end, the
status of the ï¬rst control ï¬ip-ï¬op (DATA-IN READY) indicates
if the FIFO is full, and the status of the last ï¬ip-ï¬op (DATA-
OUT READY) indicates if the FIFO contains data. As the
earliest data are removed from the bottom of the data stack
(the output end), all data entered later will automatically
propagate (ripple) toward the output.
Loading Data - Data can be entered whenever the DATA-IN
READY (DIR) ï¬ag is high, by a low to high transition on the
SHIFT-IN (SI) input. This input must go low momentarily
before the next word is accepted by the FIFO. The DIR ï¬ag
will go low momentarily, until that data have been transferred
to the second location. The ï¬ag will remain low when all 16-
word locations are ï¬lled with valid data, and further pulses
on the SI input will be ignored until DIR goes high.
Continued on next page
Pinout
CD40105BMS
TOP VIEW
3 - STATE
CONTROL
1
DIR 2
16 VDD
15 SO
SI 3
14 DOR
D0 4
13 Q0
D1 5
12 Q1
D2 6
11 Q2
D3 7
10 Q3
VSS 8
9 MR
Functional Diagram
3-STATE
CONTROL
1
4
D0
5
D1
6
D2
7
D3
3
SHIFT IN
SHIFT OUT 15
9
MASTER
RESET
13
Q0
12
Q1
11
Q2
10
Q3
14
DATA-OUT
READY
2
DATA-IN
READY
VDD = 16
VSS = 8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1317
File Number 3353
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