82C89 Datasheet, PDF (9/15 Pages) Intersil Corporation – CMOS Bus Arbiter

82C89
TABLE 1. SUMMARY OF 82C89 MODES, REQUESTING AND RELINQUISHING THE MULTI-MASTER SYSTEM BUS
SINGLE LINES FROM
80C86 OR 80C88 OR 8088
S2 S1 S0
IOB MODE
ONLY
IOB = LOW
RESB = LOW
RESB MODE ONLY
IOB = HIGH, RESB = HIGH
SYSB/RESB = SYSB/RESB =
HIGH
LOW
IOB MODE RESB MODE
IOB = LOW, RESB = HIGH
SYSB/RESB = SYSB/RESB =
HIGH
LOW
SINGLE BUS
MODE
IOB = HIGH
RESB = LOW
I/O
000
X
†
X
X
X
†
Commands 0 0 1
X
†
X
X
X
†
010
X
†
X
X
X
†
Halt
011
X
X
X
X
X
X
Memory
100
†
†
X
†
X
†
Commands 1 0 1
†
†
X
†
X
†
1 1 0†
†
†
X
†
X
†
Idle
111
X
X
X
X
X
X
NOTES:
1. X = Multi-Master System Bus is allowed to be Surrendered.
2. † = Multi-Master System Bus is Requested.
MODE
PIN
STRAPPING
MULTI-MASTER SYSTEM BUS
REQUESTED**
SURRENDERED*
Single Bus Multi-Master Mode IOB = High
RESB = Low
Whenever the processor’s status lines HLT + TI • CBRQ + HPBRQ ‡
go active
RESB Mode Only
IOB = High
RESB = High
SYSB/RESB + High •
ACTIVE STATUS
(SYSB/RESB = Low + TI) •
CBRQ + HLT + HPBRQ
IOB Mode Only
IOB = Low
RESB = Low
Memory Commands
(I/O Status + TI) • CBRQ + HLT +
HPBRQ
IOB Mode RESB Mode
IOB = Low
RESB = High
(Memory Command) •
(SYSB/RESB = High)
(I/O Status Commands) +
SYSB/RESB = Low) • CBRQ +
HPBRQ + HLT
NOTES:
* LOCK prevents surrender of Bus to any other arbiter, CRQLCK prevents surrender of Bus to any lower priority arbiter.
** Except for HALT and Passive or IDLE Status.
‡ HPBRQ, Higher priority Bus request or BPRN = 1.
1. IOB Active Low.
2. RESB Active High.
3. + is read as “OR” and • as “AND”
4. TI = Processor Idle Status S2, S1, S0 = 111
5. HLT = Processor Halt Status S2, S1, S0 = 011
4-351