82C89 Datasheet, PDF (5/15 Pages) Intersil Corporation – CMOS Bus Arbiter

82C89
Serial Priority Resolving
The serial priority resolving technique eliminates the need
for the priority encoder-decoder arrangement by daisychain-
ing the bus arbiters together, connecting the higher priority
bus arbiter’s BPRO (Bus Priority Out) output to the BPRN of
the next lower priority. See Figure 3.
BUS
ARBITER
1
BPRN
BPRO
BPRN
BUS
ARBITER
2
BPRO
BPRN
BUS
ARBITER _BPRO
3
BPRN
BUS
ARBITER BPRO
4
techniques. It allows for many arbiters to be present on the
bus while not requiring too much logic to implement.
82C89 Modes Of Operation
There are two types of processors for which the 82C89 will
provide support: An Input/Output processor (i.e. an NMOS
8089 IOP) and the 80C86, 80C88. Consequently, there are
two basic operating modes in the 82C89 bus arbiter. One,
the IOB (I/O Peripheral Bus) mode, permits the processor
access to both an I/O Peripheral Bus and a multi-master sys-
tem bus. The second, the RESB (Resident Bus mode), per-
mits the processor to communicate over both a Resident
Bus and a multi-master system bus. An I/O Peripheral Bus is
a bus where all devices on that bus, including memory, are
treated as I/O devices and are addressed by I/O commands.
All memory commands are directed to another bus, the
multi-master system bus. A Resident Bus can issue both
memory and I/O commands, but it is a distinct and separate
bus from the multi-master system bus. The distinction is that
the Resident Bus has only one master, providing full avail-
ability and being dedicated to that one master.
•
•
•
•
•
•
CBRQ BUSY
FIGURE 3. SERIAL PRIORITY RESOLVING
NOTE: The number of arbiters that may be daisy-chained together
in the serial priority resolving scheme is a function of BCLK and the
propagation delay from arbiter to arbiter. Normally, at 10MHz only 3
arbiters may be daisychained.
Rotating Priority Resolving
The rotating priority resolving technique is similar to that of
the parallel priority resolving technique except that priority is
dynamically re-assigned. The priority encoder is replaced by
a more complex circuit which rotates priority between
requesting arbiters thus allowing each arbiter an equal
chance to use the multi-master system bus, over time.
Which Priority Resolving Technique To Use
There are advantages and disadvantages for each of the
techniques described above. The rotating priority resolving
technique requires substantial external logic to implement
while the serial technique uses no external logic but can
accommodate only a limited number of bus arbiters before the
daisy-chain propagation delay exceeds the multimaster’s sys-
tem bus clock (BCLK). The parallel priority resolving tech-
nique is in general a good compromise between the other two
The IOB strapping option configures the 82C89 Bus Arbiter
into the IOB mode and the strapping option RESB config-
ures it into the RESB mode. It might be noted at this point
that if both strapping options are strapped false, the arbiter
interfaces the processor to a multi-master system bus only
(see Figure 4). With both options strapped true, the arbiter
interfaces the processor to a multi-master system bus, a
Resident Bus, and an I/O Bus.
In the IOB mode, the processor communicates and controls
a host of peripherals over the Peripheral Bus. When the I/O
Processor needs to communicate with system memory, it
does so over the system memory bus. Figure 5 shows a pos-
sible I/O Processor system configuration.
The 80C86 and 80C88 processors can communicate with a
Resident Bus and a multi-master system bus. Two bus con-
trollers and only one Bus Arbiter would be needed in such a
configuration as shown in Figure 6. In such a system config-
uration the processor would have access to memory and
peripherals of both busses. Memory mapping techniques are
applied to select which bus is to be accessed. The
SYSB/RESB input on the arbiter serves to instruct the arbi-
ter as to whether or not the system bus is to be accessed.
The signal connected to SYSB/RESB also enables or dis-
ables commands from one of the bus controllers. A sum-
mary of the modes that the 82C89 has, along with its
response to its status lines inputs, is shown in Table 1.
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