82C89 Datasheet, PDF (8/15 Pages) Intersil Corporation – CMOS Bus Arbiter

82C89
XACK
RESIDENT BUS
AEN2 AEN1
82C84A/85
CLOCK
RDY2 RDY1
READY CLK
READY CLK
S0-S2
80C86
CPU
AD0-AD15
A16-A19
STATUS
RESIDENT
COMMAND BUS
PROM
OR
DECODER
OR
CMOS HPL
(NOTE)
RESIDENT
ADDRESS BUS
CEN
AEN
S0-S2
82C88
CLK
ALE
DT/R
DEN
STB
OE
ADDR
LATCH
82C82/
82C83H
(2 OR 3)
XACK MULTI MASTER
SYSTEM BUS
S0
S1
S2
82C89
BUS
ARBITER
RESB
CLK
IOB
ANYRQST
AEN
SYSB/
RESB
MULTI MASTER
SYSTEM BUS CONTROL
V_CC
AEN
CEN
S0-S2
82C88
CLK
DT/R
DEN
IOB
ALE
MULTI MASTER
SYSTEM COMMAND BUS
OE
STB
ADDR
LATCH
82C82/
82C83H
(2 OR 3)
MULTI MASTER
SYSTEM ADDRESS BUS
RESIDENT
DATA BUS
OE
T
TRANSCEIVER
82C86H/
82C87H
(2)
T
OE
TRANSCEIVER
82C86H/
82C87H
(2)
MULTI MASTER
SYSTEM DATA BUS
FIGURE 6. 82C89 BUS ARBITER SHOWN IN SYSTEM - RESIDENT BUS CONFIGURATION
NOTE: By adding another 82C89 arbiter and connecting its AEN to the 82C88 whose AEN is presently grounded, the processor could have
access to two multi-master buses.
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