82C89 Datasheet, PDF (3/15 Pages) Intersil Corporation – CMOS Bus Arbiter

82C89
Pin Description (Continued)
PIN
SYMBOL
NUMBER
TYPE
DESCRIPTION
IOB
2
I
IO BUS: A strapping option which configures the 82C89 Arbiter to operate in systems having both
an IO Bus (Peripheral Bus) and a multi-master system bus. The arbiter requests and surrenders
the use of the multi-master system bus as a function of the status line, S2. The multi-master sys-
tem bus is permitted to be surrendered while the processor is performing IO commands and is
requested whenever the processor performs a memory command. Interrupt cycles are assumed
as coming from the peripheral bus and are treated as an IO command.
AEN
13
O
ADDRESS ENABLE: The output of the 82C89 Arbiter to the processor’s address latches, to the
82C88 Bus Controller and 82C84A or 82C85 Clock Generator. AEN serves to instruct the Bus
Controller and address latches when to three-state their output drivers.
INIT
6
I
INITIALIZE: An active low multi-master system bus input signal used to reset all the bus arbiters
on the multi-master system bus. After initialization, no arbiters have the use of the multi-master
system bus.
SYSB/RESB
3
I
SYSTEM BUS/RESIDENT BUS: An input signal when the arbiter is configured in the System/Res-
ident Mode (RESB is strapped high) which determines when the multi-master system bus is re-
quested and multi-master system bus surrendering is permitted. The signal is intended to originate
from a form of address-mapping circuitry, such as a decoder or PROM attached to the resident
address bus. Signal transitions and glitches are permitted on this pin from θ1 of T4 to θ1 of T2 of
the processor cycle. During the period from θ1 of T2 to θ1 of T4, only clean transitions are permit-
ted on this pin (no glitches). If a glitch occurs, the arbiter may capture or miss it, and the multi-mas-
ter system bus may be requested or surrendered, depending upon the state of the glitch. The
arbiter requests the multi-master system bus in the System/Resident Mode when the state of the
SYSB/RESB pin is high and permits the bus to be surrendered when this pin is low.
CBRQ
12
I/O COMMON BUS REQUEST: An input signal which instructs the arbiter if there are any other arbi-
ters of lower priority requesting the use of the multi-master system bus.
The CBRQ pins (open-drain output) of all the 82C89 Bus Arbiters which surrender to the multi-
master system bus upon request are connected together.
The Bus Arbiter running the current transfer cycle will not itself pull the CBRQ line low. Any other
arbiter connected to the CDRQ line can request the multi-master system bus. The arbiter presently
running the current transfer cycle drops its BREQ signal and surrenders the bus whenever the
proper surrender conditions exist. Strapping CBRQ low and ANYRQST high allows the multi-mas-
ter system bus to be surrendered after each transfer cycle. See the pin definition of ANYRQST.
BCLK
5
I
BUS CLOCK: The multi-master system bus clock to which all multi-master system bus interface
signals are synchronized.
BREQ
7
O
BUS REQUEST: An active low output signal in the Parallel Priority Resolving Scheme which the
arbiter activates to request the use of the multi-master system bus.
BPRN
9
I
BUS PRIORITY IN: The active low signal returned to the arbiter to instruct it that it may acquire the
multi-master system bus on the next falling edge of BCLK. BPRN active indicates to the arbiter that
it is the highest priority requesting arbiter presently on the bus. The loss of BPRN instructs the ar-
biter that it has lost priority to a higher priority arbiter.
BPRO
8
O
BUS PRIORITY OUT: An active low output signal used in the serial priority resolving scheme
where BPRO is daisy-chained to BPRN of the next lower priority arbiter.
BUSY
11
I/O BUSY: An active low open-drain multi-master system bus interface signal used to instruct all the
arbiters on the bus when the multi-master system bus is available. When the multi-master system
bus is available the highest requesting arbiter (determined by BPRN) seizes the bus and pulls
BUSY low to keep other arbiters off of the bus. When the arbiter is done with the bus, it releases
the BUSY signal, permitting it to go high and thereby allowing another arbiter to acquire the multi-
master system bus.
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