80C286 Datasheet, PDF (9/13 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

Waveforms (Continued)
80C286/883
BUS CYCLE TYPE
CLK
PCLK
(SEE NOTE 1)
V_CH
V_CL
INTR, NMI
HOLD, PEREQ
(SEE NOTE 2)
4
ERROR, BUSY
(SEE NOTE 2)
φ1 ^TX
φ2
19
19
5
4
5
V_CH
φ2
CLK
V_CL
RESET
V_CH
CLK
V_CL
RESET
φ1 ^TX φ1
φ2
7
6
(SEE NOTE 1)
T_X
φ1
φ2
φ2
7
(SEE NOTE 1)
6
NOTES:
1. PCLK indicates which processor cycle phase will occur on the
next CLK. PCLK may not indicate the correct phase until the first
cycle is performed.
2. These inputs are asynchronous. The setup and hold times shown
assure recognition for testing purposes.
NOTE:
1. When RESET meets the setup time shown, the next CLK will
start or repeat φ1 of a processor cycle.
FIGURE 3. 80C286/883 ASYNCHRONOUS INPUT SIGNAL
TIMING
FIGURE 4. 80C286/883 RESET INPUT TIMING AND SUBSE-
QUENT PROCESSOR CYCLE PHASE
BUS CYCLE TYPE
V_CH
CLK
V_CL
HILDA
T_H
φ1
φ2
16
T_H OR T_I
φ1
φ2
T_I
φ1
φ2
T_H
φ1
φ2
16
(SEE NOTE 4)
S1 • S0
PEACK
BHE, LOCK
A₂₃ - A₀,
M/IO,
COD/INTA
D₁₅ - D₀
12A (NOTE 3)
12B
IF T_S
13
(SEE NOTE 5)
IF NPX TRANSFER
VALID
14
(SEE NOTE 6)
15
(SEE NOTE 3)
15
(SEE NOTE 1)
15
(SEE NOTE 2)
15
VALID IF WRITE
PCLK
NOTES:
1. These signals may not be driven by the 80C286/883 during the time shown. The worst case in terms of latest float time is shown.
2. The data bus will be driven as shown if the last cycle before T_I in the diagram was a write T_C.
3. The 80C286/883 puts its status pins in a high impedance logic one state during T_H.
4. For HOLD request set up to HLDA, refer to Figure 8.
5. BHE and LOCK are driven at this time but will not become valid until T_S.
6. The data bus will remain in a high impedance state if a read cycle is performed.
FIGURE 5. EXITING AND ENTERING HOLD
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