80C286 Datasheet, PDF(11/13 Page) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

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80C286 Datasheet, PDF (11/13 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

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80C286/883

Waveforms (Continued)

BUS CYCLE TYPE

CLK

HOLD

BUS HOLD ACKNOWLEDGE

Ï1 Ï2

WRITE CYCLE

Ï1 Ï2

BUS HOLD

ACKNOWLEDGE

Ï1 Ï2

(SEE NOTE 4)

(SEE NOTE 5)

(SEE NOTE 6)

HLDA

(SEE NOTE 1)

S1 â¢ S0

A23 - A0

M/IO,

COD/INTA

BHE, LOCK

VALID

(SEE NOTE 2)

(SEE NOTE 3)

(SEE NOTE 1)

D15 - D0

SRDY +

SRDYEN

ARDY +

ARDYEN

CMDLY

MWTC

VOH

DT/R

DEN

VALID

NOT READY NOT READY (SEE NOTE 7)

NOT READY NOT READY

READY

DELAY ENABLE

(SEE NOTE 7)

ALE

TS - STATUS CYCLE

CT - COMMAND CYCLE

NOTES:

1. Status lines are held at a high impedance logic one by the 80C286 during a HOLD state.

2. Address, M/IO and COD/lNTA may start floating during any TC depending on when internal 80C286 bus arbiter decides to release bus to

external HOLD. The float starts in Ï2 of TC.

3. BHE and LOCK may start floating after the end of any TC depending on when internal 80C286 bus arbiter decides to release bus to ex-

ternal HOLD. The float starts in Ï1 of TC.

4. The minimum HOLD to HLDA time is shown. Maximum is one TH longer.

5. The earliest HOLD time is shown. It will always allow a subsequent memory cycle if pending is shown.

6. The minimum HOLD to HLDA time is shown. Maximum is a function of the instruction, type of bus cycle and other machine state (i.e.,

Interrupts, Waits, Lock, etc.).

7. Asynchronous ready allows termination of the cycle. Synchronous ready does not signal ready in this example. Synchronous ready state

is ignored after ready is signaled via the asynchronous input.

FIGURE 8. MULTIBUS WRITE TERMINATED BY ASYNCHRONOUS READY WITH BUS HOLD

3-138

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