X79000 Datasheet, PDF (8/18 Pages) Intersil Corporation – NV DAC with Selectable Output Range and Memory

SPI INPUT TIMING
X79000, X79001, X79002
CS
SCK
SI
SO
t_LEAD
t_SU
t_H
t_WL
MSB
High Impedance
t_CYC
...
t_WH
t_FI
...
t_CS
t_RI
LSB
t_LAG
SPI INTERFACE TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall times, between 10% and 90%
Input and Output Timing Threshold Level
External Load at pin SO
10% to 90% of Vcc
10ns
1.4V
2.6kΩ to Vcc, 3.03kΩ to Vss, and 10pF to Vss
SERIAL INPUT TIMING
Symbol
f_SCK
t_CYC
t_WH
t_WL
t_LEAD
t_LAG
t_SU
t_H
t_RI ⁽¹⁾
t_FI ⁽¹⁾
t_CS
t_WC ⁽²⁾
Parameter
Clock Frequency
Cycle Time
Clock HIGH Time
Clock LOW Time
CS Lead Time
CS Lag Time
Data Setup Time
Data Hold Time
Input Rise Time
Input Fall Time
CS Deselect Time
Non-volatile Write Cycle Time
Min.
200
80
80
100
100
20
20
100
Max.
5
20
20
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Notes: 1. These parameters are periodically sampled and not 100% tested.
2. t_WC is the time from the rising edge of CS after a valid nonvolatile write sequence, to the end of the self-timed internal non-volatile write
cycle. It is the minimum cycle time to be allowed for any non-volatile write cycle by the user, unless the “WIP” bit is used to check for the
end of the write cycle.
8
FN8147.0
March 17, 2005