X79000 Datasheet, PDF (11/18 Pages) Intersil Corporation – NV DAC with Selectable Output Range and Memory

X79000, X79001, X79002
FUNCTIONAL DESCRIPTION
DAC Register Clear Function
When the input pin CLR is set to logic high, the DAC
volatile register and serial input registers are reset to 000
hex. CLR is an asynchronous input. CLR has an on-chip
pulldown. CLR is ignored while RDY is high.
Buffer Output Enable Function
When the input pin OE is set to logic low, the DAC
buffered output, Vbuf, is set to high impedance.
When the input pin OE is at a logic high, the DAC
buffered output is enabled.
UP/DOWN Interface
The UP/DOWN Interface can be used to change the
value of the DAC register without using the serial
Interface.
The CS pin must be HIGH, when the UP/DOWN
Interface is used, to set the serial interface in standby
mode.
Control bits Count8 and Count10 determine the binary
word that is incremented or decremented, according to
the following table:
Count8
0
0
1
1
Count10
Part of DAC register
incremented or
decremented.
0
The complete 12 bit word is used
1
10 MSBs are used
0
8 MSBs are used
1
Reserved
These control bits are set by performing a Write
Operation with the serial interface prior to operation of
the UP/DOWN interface.
For example, when Count8 is one, the DAC register
is affected by increment or decrement operations as
follows:
8 MSBs
1000 1011
1000 1010
1000 1001
1000 1000
1000 0111
4 LSBs
1110
1110
1110
1110
1110
Increment
Increment
Initial Value
Decrement
Decrement
A HIGH to LOW transition on the UP pin, while the
DOWN pin is LOW, increments the selected binary word
by one.
A HIGH to LOW transition on the DOWN pin, while
the UP pin is LOW, decrements the selected binary
word by one.
Other combinations are not valid. See the following table
for a summary of these operations.
CS Up Down
L
X
X
Mode
SPI Control
H
L
Increment
H
L
Decrement
H
H
Not Allowed
H
H
Not Allowed
X = Don’t Care
RDY Pin
The RDY pin is an open drain output which will follow the
V_CC voltage on power-up (due to the pullups) resistor
and will transition to a low state at time t_RDY after V_CC
reaches a minimum voltage (V_RDY). As long as V_CC is
higher the V_RDY, the output will remain low. If V_CC falls
below V_RDY, the RDY output will return to a high state.
11
FN8147.0
March 17, 2005