X79000 Datasheet, PDF (6/18 Pages) Intersil Corporation – NV DAC with Selectable Output Range and Memory

X79000, X79001, X79002
Symbol
V_POR
V_RDY
T_RDY
Parameter
Power-on reset threshold voltage
RDY indicator minimum voltage
RDY indicator delay
Min Typ Max Unit
Test Conditions / Notes
1.5
2.8
V
2.6
2.8
V See figure 1.
100
6000 µs 2kΩ and 100pF between Vcc and
RDY ⁽⁴⁾
Notes: 1. INL, DNL, Offset Error and Full Scale error measured at Vbuf with VFB connected to Vbuf.
2. The V_L and V_H levels are set using the configuration register according to the following table:
Address VH2
VH1
VH0
VL2
VL1
VL0
Count 8 Count 10
3Ch
1
0
1
0
0
1
X
X
X = don’t care
This setting corresponds to the nominal values of V_H = 3.025V and V_L = 0.151V
3. INL is measured at the maximum range of (V_H-V_L). INL varies inversely with the range of (V_H-V_L). DNL increases at lower
(V_H-V_L) ranges but the DAC retains montonicity.
4. Total offset error scales with V_L according to (1% x V_L) + 10mV and total full scale error scales with V_H according to (1% x V_H) + 10mV
5. Guaranteed by characterization, not 100% tested.
6. f_SCK = 5MHz, using SPI interface test conditions on pg. 8.
ENDURANCE AND DATA RETENTION (V_CC = 5V ±10%, T_A = Full Operating Temprature Range)
Parameter
Minimum endurance
100,000
Data changes per bit
Data retention
10
Years
FIGURE 1. RDY PIN TIMING
V_RDY
V_CC
0V
Time
V_(RDY)
T_RDY
SYMBOL TABLE
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from Low to
High
May change
from High to
Low
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from Low to
High
Will change
from High to
Low
Changing:
State Not
Known
Center Line
is High
Impedance
Device
Ready
Power-down
Device Disabled
Time
Vbuf OUTPUT ENABLE TIMING
OE
V_OUT
t_OEDIS
t_OEVALID
V_{buf = High Impedance}
6
FN8147.0
March 17, 2005