X79000 Datasheet, PDF (14/18 Pages) Intersil Corporation – NV DAC with Selectable Output Range and Memory

X79000, X79001, X79002
READ OPERATION
A Read Operation is selected when the R/W bit in the
Identification Byte is set to “1”. During a Read Operation,
the X79000 transmits Data Bytes at pin SO, starting at
the first falling edge of SCK, following the rising edge of
SCK that samples the LSB of the Memory Address Byte.
The transmission continues until the CS pin signal goes
HIGH. The Data Bytes are from the memory location
indicated by an internal pointer. This pointer initial value
is the value of the Memory Address Byte, and increments
by one during transmission of each Data Byte. After
reaching memory location 3Fh, the pointer “rolls over” to
00h, and then it continues incremented by one during
each following Data Byte transmission.
If bit “NVDAC” is “1” when reading from byte addresses
38h or 39h, the output is the content of the non-volatile
DAC initial value register. If bit “NVDAC” is “0”, the output
is the current value in the volatile DAC register. See the
next section for writing bit “NVDAC”.
WRITE OPERATION
A “Write Operation” is selected when the R/W bit in the
Identification Byte is set to “0”. The memory array of the
X79000 is organized in 8 pages of 8 bytes each. A single
write operation can be used to write between 1 to 8 bytes
within the same page.
During a Write Operation, the Data Bytes are transmitted
immediately following the Memory Address Byte.
The Data Bytes are written to the memory location
indicated by an internal pointer. This pointer initial value
is the value of the Memory Address Byte, and increments
by one during reception of each Data Byte. After
reaching the highest memory location within a page, the
pointer “rolls over” to the lowest memory location of that
page. The page address remains constant during a
single write operation.
For example, if the Write operation includes 6 Data
Bytes, and the Memory Address byte is 5 (decimal), the
first 3 bytes are written to locations 5, 6, and 7, while the
last 3 bytes are written to locations 0, 1, and 2. If the write
operation includes more than 8 Data Bytes, the new data
overwrites the previous data, one byte at a time.
Bytes at locations 38h through 3Fh are special cases.
Bytes at locations 3Ah, 3Bh, 3Dh, and 3Eh, are reserved
and must not be written. Reserved bits in other bytes
must be set to “0” if writing to those bytes, and should be
ignored when read. The DAC register Bytes at locations
38h & 39h must be written together in a single 2-Byte
write operation.
Location 3Fh contains the “NVDAC” bit. If bit “NVDAC” is
“1”, the values of DAC[11:0] are written to non-volatile
memory, otherwise they are written into volatile registers.
Bit “NVDAC” is a volatile bit that has a “0” value at power-
up. The “NVDAC” bit is set to “1” by writing 80h to byte
location 3Fh. It is reset to “0” when the device is powered
down or by writing 00h to byte location 3Fh.
The conifiguration byte at location 3Ch must be written
as a single byte.
NON VOLATILE WRITE:
After a complete write command sequence is correctly
received by the device, and if the write operation is to
non volatile memory, then the X79000 enters an internal
high voltage write cycle that last up to 10 ms.
The internal write cycle starts at the rising edge of CS
that completes the write instruction sequence. The
progress of this internal operation can be monitored
through the “Write In Progress”, WIP, bit. The WIP bit
is “1” during the internal write cycle and it’s “0”
otherwise. The WIP bit is read with a “Write Status
Polling Command”.
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FN8147.0
March 17, 2005