X5648 Datasheet, PDF (8/18 Pages) Intersil Corporation – CPU Supervisor with 64Kbit SPI EEPROM

Figure 6. Read Status Register Sequence
CS
X5648, X5649
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Instruction
SI
High Impedance
SO
Data Out
76543210
MSB
Figure 7. Write Enable Latch Sequence
CS
SCK
01234567
SI
High Impedance
SO
8
FN8136.0
March 17, 2005