X5648 Datasheet, PDF (1/18 Pages) Intersil Corporation – CPU Supervisor with 64Kbit SPI EEPROM

®
Data Sheet
X5648, X5649
(Replaces X25648, X25649)
March 17, 2005
FN8136.0
CPU Supervisor with 64Kbit SPI EEPROM
FEATURES
• Low V_CC detection and reset assertion
—Five standard reset threshold voltages
—Re-program low V_CC reset threshold voltage
using special programming sequence
—Reset signal valid to V_CC = 1V
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
—<400µA max active current during read
• 64Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
Block Lock^™ protection
—In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—32-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
—14-lead SOIC, 8-lead PDIP
BLOCK DIAGRAM
DESCRIPTION
These devices combine three popular functions, Power-
on Reset Control, Supply Voltage Supervision, and Block
Lock Protect Serial EEPROM Memory in one package.
This combination lowers system cost, reduces board
space requirements, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The device’s low V_CC detection circuitry protects the
user’s system from low voltage conditions by holding
RESET/RESET active when V_CC falls below a minimum
V_CC trip point. RESET/RESET remains asserted until
V_CC returns to proper operating level and stabilizes. Five
industry standard V_TRIP thresholds are available,
however, Intersil’s unique circuits allow the threshold to
be reprogrammed to meet custom requirements or to
fine-tune the threshold in applications requiring higher
precision.
WP
SI
SO
SCK
CS
Data
Register
Command
Decode &
Control
Logic
Protect Logic
Status
Register
16Kbits
16Kbits
32Kbits
V_CC
+
V_TRIP
-
Reset
Timebase
Power-on and
Low Voltage
Reset
Generation
RESET/RESET
X5648 = RESET
X5649 = RESET
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright Intersil Americas Inc. 2005. All Rights Reserved
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