X5648 Datasheet, PDF (11/18 Pages) Intersil Corporation – CPU Supervisor with 64Kbit SPI EEPROM

X5648, X5649
EQUIVALENT A.C. LOAD CIRCUIT AT 5V V_CC
5V
5V
2.06kΩ
4.6kΩ
Output
3.03kΩ
RESET/RESET
100pF
30pF
A.C. TEST CONDITIONS
Input pulse levels
Input rise and fall times
Input and output timing level
V_CC x 0.1 to V_CC x 0.9
10ns
V_CC x 0.5
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Serial Input Timing
Symbol
f_SCK
t_CYC
t_LEAD
t_LAG
t_WH
t_WL
t_SU
t_H
t_RI(3)
t_FI(3)
t_CS
t_WC(4)
Clock frequency
Cycle time
CS lead time
CS lag time
Clock HIGH time
Clock LOW time
Data setup time
Data hold time
Input rise time
Input fall time
CS deselect time
Write cycle time
Parameter
2.7-5.5V
Min.
Max.
0
2
500
250
250
200
250
50
50
100
100
500
10
Serial Input Timing
t_CS
CS
t_LEAD
t_LAG
SCK
t_SU
t_H
t_RI
t_FI
SI
MSB IN
LSB IN
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
SO
High Impedance
11
FN8136.0
March 17, 2005