X1288 Datasheet, PDF (8/27 Pages) Xicor Inc. – 2-Wire RTC Real Time Clock/Calendar/CPU Supervisor with EEPROM

V_TRIP Programming Timing Diagram
V_CC
(V_TRIP)
X1288
V_TRIP
t_TSU
t_THD
RESET
V_CC
SCL
SDA
t_VPS
0 123456 7
V_P = 15V
01 234567 0 123456 7
t_VPH
01234 567
AEh
00h
03h/01h
00h
t_VPO
V_CC
t_RP
V_TRIP Programming Parameters
Parameter
Description
t_VPS
t_VPH
t_TSU
t_THD
t_VPO
V_TRIP Program Enable Voltage Setup time
V_TRIP Program Enable Voltage Hold time
V_TRIP Setup time
V_TRIP Hold (stable) time
V_TRIP Program Enable Voltage Off time
(Between successive adjustments)
t_RP
V_TRIP Program Recovery Period
(Between successive adjustments)
V_P
V_TRAN
V_tv
Programming Voltage
V_TRIP Programmed Voltage Range
V_TRIP Program variation after programming
(Programmed at 25°C)
V_TRIP programming parameters are not 100% Tested.
DESCRIPTION
The X1288 device is a Real Time Clock with
clock/calendar, two polled alarms with integrated 32kx8
EEPROM, oscillator compensation, CPU Supervisor
(POR/LVS and WDT) and battery backup switch.
The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving board
area and component cost.
The Real-Time Clock keeps track of time with separate
registers for Hours, Minutes, Seconds and 1/100 of a
second. The Calendar has separate registers for Date,
Month, Year and Day-of-week. The calendar is correct
through 2099, with automatic leap year correction.
Min.
1
1
1
10
0
10
14
1.7
-25
Max.
16
5.0
+25
Units
µs
µs
µs
ms
µs
ms
V
V
mV
The powerful Dual Alarms can be set to any
Clock/Calendar value for a match. For instance, every
minute, every Tuesday, or 5:23 AM on March 21. The
alarms can be polled in the Status Register or provide a
hardware interrupt (IRQ Pin). There is a repeat mode for
the alarms allowing a periodic interrupt.
The PHZ/IRQ pin may be software selected to provide a
frequency output of 1 Hz, 100 Hz, or 32,768 Hz.
The X1288 device integrates CPU Supervisor func-tions
and a Battery Switch. There is a Power-On Reset
(RESET output) with typically 250 ms delay from power-
on. It will also assert RESET when Vcc goes below the
specified threshold. The Vtrip threshold is user repro-
grammable. There is a WatchDog Timer (WDT) with 3
selectable time-out periods (0.25s, 0.75s, 1.75s) and a
disabled setting. The watchdog activates the RESET pin
when it expires.
8
FN8102.3
April 14, 2006