X1288 Datasheet, PDF (17/27 Pages) Xicor Inc. – 2-Wire RTC Real Time Clock/Calendar/CPU Supervisor with EEPROM

X1288
SCL
SDA
Start
Stop
FIGURE 9. VALID START AND STOP CONDITIONS
SCL from
Master
1
Data Output
from Transmitter
Data Output
from Receiver
Start
8
9
Acknowledge
FIGURE 10. ACKNOWLEDGE RESPONSE FROM RECEIVER
Array
CCR
Device Identifier
1
1
0
1
1
0
0
1
1
1
Slave Address Byte
1
R/W _{Byte 0}
0 A14 A13 A12 A11 A10 A9
Word Address 1
A8 _{Byte 1}
Word Address 0
A7
A6
A5
A4
A3
A2
A1
A0
Byte 2
Data Byte
D7
D6
D5
D4
D3
D2
D1
D0
Byte 3
FIGURE 11. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES (128 BYTE PAGES)
17
FN8102.3
April 14, 2006