X1288 Datasheet, PDF (23/27 Pages) Xicor Inc. – 2-Wire RTC Real Time Clock/Calendar/CPU Supervisor with EEPROM

X1288
Table 7. Crystal Parameters Required for Intersil RTC’s
Parameter
Min
Typ
Max
Frequency
32.768
Freq. Tolerance
±100
Turnover Temperature
20
25
30
Operating Temperature Range
Parallel Load Capacitance
Equivalent Series Resistance
-40
85
12.5
50
Units
kHz
ppm
°C
°C
pF
kΩ
Notes
Down to 20ppm if desired
Typically the value used for most
crystals
For best oscillator performance
Table 8. Crystal Manufacturers
Manufacturer
Part Number
Citizen
CM201, CM202, CM200S
Epson
Raltron
MC-405, MC-406
RSM-200S-A or B
SaRonix
32S12A or B
Ecliptek
ECS
ECPSM29T-32.768K
ECX-306/ECX-306I
Fox
FSM-327
A final application for the ATR control is in-circuit cali-
bration for high accuracy applications, along with a
temperature sensor chip. Once the RTC circuit is pow-
ered up with battery backup, the PHZ output is set at
32.768kHz and frequency drift is measured. The ATR
control is then adjusted to a setting which minimizes
drift. Once adjusted at a particular temperature, it is
possible to adjust at other discrete temperatures for
minimal overall drift, and store the resulting settings in
the EEPROM. Extremely low overall temperature drift
is possible with this method. The Intersil evaluation
board contains the circuitry necessary to implement
this control.
For more detailed operation see Intersil’s application
note AN154 on Intersil’s website at www.intersil.com.
Layout Considerations
The crystal input at X1 has a very high impedance and
will pick up high frequency signals from other circuits
on the board. Since the X2 pin is tied to the other side
of the crystal, it is also a sensitive node. These signals
can couple into the oscillator circuit and produce dou-
ble clocking or mis-clocking, seriously affecting the
accuracy of the RTC. Care needs to be taken in layout
of the RTC circuit to avoid noise pickup. Below in Fig-
ure 19 is a suggested layout for the X1286 or X1288
devices.
Temp Range
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-10 to +60°C
-10 to +60°C
-40 to +85°C
+25°C Freq Toler.
±20ppm
±20ppm
±20ppm
±20ppm
±20ppm
±20ppm
±20ppm
C1
0.1µF
XTAL1
32.768kGz
R1 10k
U1
X1286/X1288
FIGURE 19. SUGGESTED LAYOUT FOR INTERSIL RTC IN SO-8
The X1 and X2 connections to the crystal are to be
kept as short as possible. A thick ground trace around
the crystal is advised to minimize noise intrusion, but
ground near the X1 and X2 pins should be avoided as
it will add to the load capacitance at those pins. Keep
in mind these guidelines for other PCB layers in the
vicinity of the RTC device. A small decoupling capaci-
tor at the Vcc pin of the chip is mandatory, with a solid
connection to ground.
The X1286 product has a special consideration. The
PHZ/IRQ- pin on the 8-lead SOIC package is located
next to the X2 pin. When this pin is used as a fre-
quency output (PHZ) and is set to 32.768kHz output
frequency, noise can couple to the X1 or X2 pins and
cause double-clocking. The layout in Figure 19 can
help minimize this by running the PHZ output away
23
FN8102.3
April 14, 2006