ISL6540A Datasheet, PDF (8/22 Pages) Intersil Corporation – Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability

ISL6540A
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Parts are 100% tested at +25°C. Temperature
limits established by characterization and are not production tested. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
VIN_{DV/DT_Max} Maximum VIN DV/DT
EXTERNAL LINEAR REGULATOR
V_IN = 0 V to V_IN step, PVCC < 2.0V at V_IN
-
application; V_IN > 6.5V
V_IN = 2.0 V to V_IN step, 2.0V < PVCC at V_IN
-
application; V_IN > 6.5V
1
0.05
-
V/µs
-
V/µs
LIN_DRV Maximum Sinking Drive Current LIN_DRV = VIN = 20V
1.30
4.17
5.30
mA
LIN_DRV = VIN = 3.3V
1.67
3.88
4.67
mA
OPERATIONAL TRANSCONDUCTANCE AMPLIFIER (OTA)
DC Gain
Drive Capability
GATE DRIVERS
C_SS = 0.1µF, at SS Pin
C_SS = 0.1µF, at SS Pin
-
88
30
37
-
dB
44
µA
R_UGATE Ugate Source Resistance
500mA Source Current, PVCC = 5.0V
I_UGATE
Ugate Source Saturation Current V_UGATE-PHASE = 2.5V, PVCC = 5.0V
R_UGATE Ugate Sink Resistance
500mA Sink Current, PVCC = 5.0V
I_UGATE
Ugate Sink Saturation Current V_UGATE-PHASE = 2.5V, PVCC = 5.0V
R_LGATE Lgate Source Resistance
500mA Source Current, PVCC = 5.0V
I_LGATE
Lgate Source Saturation Current V_LGATE = 2.5V, PVCC = 5.0V
R_LGATE Lgate Sink Resistance
500mA Sink Current, PVCC = 5.0V
I_LGATE
Lgate Sink Saturation Current V_LGATE = 2.5V, PVCC = 5.0V
OVERCURRENT PROTECTION (OCP)
-
1.0
-
2.0
-
1.0
-
2.0
-
1.0
-
2.0
-
0.4
-
4.0
-
Ω
-
A
-
Ω
-
A
-
Ω
-
A
-
Ω
-
A
I_LSOC
Low Side OCP (LSOC) Current LSOC = 0V to VCC - 1.0V, T_A = 0°C to +70°C
86
100
107
µA
Source
LSOC = 0V to VCC - 1.0V, T_A = -40°C to +85°C
84
100
109
µA
I_{LSOC_OFSET} LSOC Maximum Offset Error
VCC = 2.9V and 5.6V T_SAMPLE < 10µs
-
±2
-
mV
I_HSOC
High Side OCP (HSOC) Current HSOC = 0.8V to 22V T_A = 0°C to +70°C
Source
HSOC = 0.8V to 22V T_A = -40°C to +85°C
91
100
106
µA
89
100
107
µA
I_{HSOC_LOW}
HSOC = 0.3V to 0.8V
84
-
107
µA
I_{HSOC_OFSET} HSOC Maximum Offset Error
VCC = 2.9V and 5.5V T_SAMPLE < 10µs
-
±2
-
mV
MARGINING CONTROL
V_MARG
Minimum Margining Voltage of
Internal Reference
R_MARG = 10kΩ, R_OFS- = 6.01kΩ,
MAR_CRTL = 0V
-187
-197
-209
mV
V_MARG
Maximum Margining Voltage of R_MARG = 10kΩ, R_OFS+ = 6.01kΩ,
Internal Reference
MAR_CRTL = VCC
185
197
208
mV
N_MARG Margining Transfer Ratio
MAR_CTRL ^{Positive Margining Threshold}
MAR_CTRL ^{Negative Margining Threshold}
MAR_CTRL ^{Tri-state Input Level}
POWER GOOD MONITOR
N_MARG = (V_OFS--V_OFS+)/V_MARG
Disable Mode
4.84
5
1.51
1.8
0.75
0.9
1.21
1.325
5.22
SDR
2.02
V
1.05
V
1.40
V
V_UVR
V_UVF
V_OVR
V_OVF
T_{PG_DLY}
I_{PG_DLY}
Undervoltage Rising Trip Point
Undervoltage Falling Trip Point
Overvoltage Rising Trip Point
Overvoltage Falling Trip Point
PGOOD Delay
PGOOD Delay Source Current
C_{PG_DLY} = 0.1µF
-7%
-13%
13%
7%
-
17
-9%
-15%
15%
9%
7.1
21
-11%
V_SS
-17%
V_SS
17%
V_SS
11%
V_SS
-
ms
24
µA
8
FN6288.5
October 7, 2008