ISL6540A Datasheet, PDF (11/22 Pages) Intersil Corporation – Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability

ISL6540A
OV/UV/PGOOD comparators. The VMON pin should be
connected to the FB pin by a standard feedback network. In
the event of the remote sense buffer is disabled, the VMON
pin should be connected to VOUT by a resistor divider along
with FB’s compensation network. An RC filter should be
used if VMON is to be connected directly to FB instead of to
VOUT through a separate resistor divider network.
GND (Bottom Side Pad, Analog Ground)
Signal ground for the IC. All voltage levels are measured
with respect to this pin. This pin should not be left floating.
Functional Description
Initialization
The ISL6540A automatically initializes upon receipt of power
without requiring any special sequencing of the input
supplies. The Power-On Reset (POR) function continually
monitors the input supply voltages (PVCC, VFF, VCC) and
the voltage at the EN pin. Assuming the EN pin is pulled to
above ~0.50V, the POR function initiates soft-start operation
after all input supplies exceed their POR thresholds.
HIGH = ABOVE POR; LOW = BELOW POR
VCC POR
VFF POR
PVCC POR
EN POR
AND
SOFT-START
FIGURE 1. SOFT-START INITIALIZATION LOGIC
VIN
R_UP
R_EN
1kΩ
R_DOWN
V_{EN_REF}
EN
SYS_ENABLE
I_{EN_HYS}=10µA
R_UP
=
V_{-----E----N----_---H----Y---S--}
I _{E N _HYS}
–
1
kΩ
R_DOWN
=
(_---R_{-----U----P-----+-----}1_---k_----Ω_-----)_---•_-----V_{----E----N----_---R----E---F--}
V_{EN_FTH} – V_{EN_REF}
V_{EN_FTH} = V_{EN_RTH} – V_{EN_HYS}
FIGURE 2. ENABLE POR CIRCUIT
With all input supplies above their POR thresholds, driving
the EN pin above 0.50V initiates a soft-start cycle. In addition
to normal TTL logic, the enable pin can be used as a voltage
monitor with programmable hysteresis through the use of the
internal 10µA sink current and an external resistor divider.
This feature is especially designed for applications that have
input rails greater than a 3.3V and require a specific input rail
POR and Hysteresis levels for better undervoltage
protection. Consider for a 12V application choosing
R_UP = 97.6kΩ and R_DOWN = 5.76kΩ there by setting the
rising threshold (V_{EN_RTH}) to ~10V and the falling threshold
(V_{EN_FTH}) to ~9V, for ~1V of hysteresis (V_{EN_HYS}). Care
should be taken to prevent the voltage at the EN pin from
exceeding VCC when using the programmable UVLO
functionality.
Soft-Start
The POR function activates the internal 37µA OTA which
begins charging the external capacitor (C_SS) on the SS pin to a
target voltage of VCC. The ISL6540A’s soft-start logic continues
to charge the SS pin until the voltage on COMP exceeds the
bottom of the oscillator ramp, at which point, the driver outputs
are enabled with the low side MOSFET first being held low for
200ns to provide for charging of the bootstrap capacitor. Once
the driver outputs are enabled, the OTA’s target voltage is then
changed to the margined (if margining is being used) reference
voltage (V_{REF_MARG}), and the SS pin is ramped up or down
accordingly. This method reduces start-up surge currents due
to a pre-charged output by inhibiting regulator switching until
the control loop enters its linear region. By ramping the positive
input of the error amplifier to VCC and then to V_{REF_MARG}, it is
even possible to mitigate surge currents from outputs that are
pre-charged above the set output voltage. As the SS pin
connects directly to the non-inverting input of the error amplifier,
noise on this pin should be kept to a minimum through careful
routing and part placement. To prevent noise injection into the
error amplifier the SS capacitor should be located within 150
mils of the SS and GND pins. Soft-start is declared done when
the drivers have been enabled and the SS pin is within ±3mV of
V_{REF_MARG}.
VMON
+15%
+9%
V_{REF_MARG}
-9%
-15%
GOOD
UV
OV
GOOD
UV
FIGURE 3. UNDERVOLTAGE-OVERVOLTAGE WINDOW
T_{PG_DLY} = C_{PG_DLY} ⋅ ¹-₂---^.1--⁴--_μ-⁹---_A-^V--
(EQ. 1)
11
FN6288.5
October 7, 2008