ISL6540A Datasheet, PDF (13/22 Pages) Intersil Corporation – Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability

ISL6540A
point varies mainly due to the MOSFETs r_DS(ON) variations
and system noise. To avoid overcurrent tripping in the
normal operating load range, find the R_HSOC and/or R_LSOC
resistor from the previous detailed equations with:
1. Maximum r_DS(ON) at the highest junction temperature.
2. Minimum I_LSOC and/or I_HSOC from specification table on
page 8.
3. Determine the overcurrent trip point greater than the
maximum output continuous current at maximum
inductor ripple current.
Frequency Programming
By tying a resistor to GND from FS pin, the switching
frequency can be set between 250kHz and 2MHz.
Oscillator/VFF
The Oscillator is a triangle waveform, providing for leading
and falling edge modulation. The bottom of the oscillator
waveform is set at 1.0V. The ramp's peak-to-peak amplitude
is determined from the voltage on the VFF (Voltage
Feed-Forward) pin. See Equation 6:
ΔVosc = 0.16 • VFF
(EQ. 6)
An internal RC filter of 233kΩ and 2pF (341kHz) provides
filtering of the VFF voltage. An external RC filter may be
required to augment this filter in the event that it is
insufficient to prevent noise injection or control loop
interactions. Voltages below 2.9V on the VFF pin may result
in undesirable operation due to extremely small peak to
peak oscillator waveforms. The oscillator waveform should
not exceed VCC -1.0V. For high VFF voltages the
internal/external 5.5V linear regulator should be used. 5.5V
on VCC provides sufficient headroom for 100% duty cycle
operation when using the maximum VFF voltage of 22V. In
the event of sustained 100% duty cycle operation, defined as
32-clock cycles where no LG pulse is detected, LG will be
pulsed on to refresh the design’s bootstrap capacitor.
80
60
40
30
20
10
7
5
200k 300k 400k
600k 800k 1M
2M
FREQUENCY (Hz)
FIGURE 4. R_FS RESISTANCE vs FREQUENCY
Fs[Hz] ≈ 1.178×10¹⁰ • R_T[Ω]^–0.973 (R_T TO GND) ^{(EQ. 7)}
Internal Series Linear Regulator
The VIN pin is connected to PVCC with a 2Ω internal series
linear regulator, which is internally compensated. The
external series linear regulator option should be used for
applications requiring pass elements of less than 2Ω. When
using the internal regulator, the LIN_DRV pin should be
connected directly to GND. The PVCC and VIN pins should
have a bypass capacitor (at least 10µF on PVCC is required)
connected to PGND. For proper operation the PVCC
capacitor must be within 150 mils of the PVCC and the
PGND pins, and be connected to these pins with dedicated
traces. The internal series linear regulator’s input (VIN) can
range between 3.3V to 20V ±10%. The internal linear
regulator is to provide power for both the internal MOSFET
drivers through the PVCC pin and the analog circuitry
through the VCC pin. The VCC pin should be connected to
the PVCC pin with an RC filter to prevent high frequency
driver switching noise from entering the analog circuitry.
When VIN drops below 5.5V, the pass element will saturate;
PVCC will track VIN, minus the dropout of the linear
regulator: PVCC = VIN-2xI_VIN. When used with an external
5V supply, the VIN pin should be tied directly to PVCC.
At start-up (PVCC = 0V and VIN = 0V) the DV/DT on VIN
should be kept below 1V/µs to prevent electrical overstress
on PVCC. Care should be taken to keep the DV/DT on VIN
below 0.05V/µs if the initial steady state voltage on PVCC is
above 2.0V, as electrical overstress on PVCC is otherwise
possible.
External Series Linear Regulator
The LIN_DRV pin provides sinking drive capability for an
external pass element linear regulator controller. The
external linear options are especially useful when the
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FN6288.5
October 7, 2008