ISL6540A Datasheet, PDF(18/22 Page) Intersil Corporation – Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability

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ISL6540A Datasheet, PDF (18/22 Pages) Intersil Corporation – Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability

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ISL6540A

COMP

E/A +

VREF

VMON

RFB

VSEN-

CSEN ROS

VSEN+

PWM

CIRCUIT

OSCILLATOR

VOSC

HALF-BRIDGE

DRIVE

VOUT

VIN

UGATE

PHASE

LGATE

DCR

ESR

ISL6540A EXTERNAL CIRCUIT

FIGURE 9. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

Figure 9 highlights the voltage-mode control loop for a

synchronous-rectified buck converter, when using an internal

differential remote sense amplifier. The output voltage

(VOUT) is regulated to the reference voltage, VREF, level.

The error amplifier output (COMP pin voltage) is compared

with the oscillator (OSC) triangle wave to provide a

pulse-width modulated wave with an amplitude of VIN at the

PHASE node. The PWM wave is smoothed by the output

filter (L and C). The output filter capacitor bankâs equivalent

series resistance is represented by the series resistor ESR.

The modulator transfer function is the small-signal transfer

function of VOUT/VCOMP. This function is dominated by a

DC gain, given by DMAXVIN/VOSC, and shaped by the

output filter, with a double pole break frequency at FLC and a

zero at FCE. For the purpose of this analysis C and ESR

represent the total output capacitance and its equivalent

series resistance.

FLC

-------------1--------------

2Ï â L â C

FCE

----------------1-----------------

2Ï â C â ESR

(EQ. 10)

The compensation network consists of the error amplifier

(internal to the ISL6540A) and the external R1 thru R3, C1 thru

C3 components. The goal of the compensation network is to

provide a closed loop transfer function with high 0dB crossing

frequency (F0; typically 0.1 to 0.3 of FSW) and adequate

phase margin (better than 45Â°). Phase margin is the

difference between the closed loop phase at F0dB and 180Â°.

The equations that follow relate the compensation networkâs

poles, zeros and gain to the components (R1, R2, R3, C1, C2,

and C3) in Figures 7 and 9. Use the following guidelines for

locating the poles and zeros of the compensation network:

1. Select a value for R1 (1kÎ© to 10kÎ©, typically). Calculate

value for R2 for desired converter bandwidth (F0). If

setting the output voltage to be equal to the reference set

voltage as shown in Figure 7, the design procedure can

be followed as presented. However, when setting the

output voltage via a resistor divider placed at the input of

the differential amplifier (as shown in Figure 9), in order

to compensate for the attenuation introduced by the

resistor divider, the below obtained R2 value needs be

multiplied by a factor of (ROS+RFB)/ROS. The remainder

of the calculations remain unchanged, as long as the

compensated R2 value is used.

----V----O----S----C-----â---R-----1----â---F----0-----

dMAX â VIN â FLC

(EQ. 11)

A small capacitor, CSEN in Figure 9, can be added to filter

out noise, typically CSEN is chosen so the corresponding

time constant does not reduce the overall phase margin

of the design, typically this is 2x to 10x switching

frequency of the regulator. As the ISL6540A supports

100% duty cycle, dMAX equals 1. The ISL6540A also

uses feedforward compensation, as such VOSC is equal

to 0.16 multiplied by the voltage at the VFF pin. When

tieing VFF to VIN, the Equation 12 simplifies to:

0----.--1---6-----â---R----1-----â---F----0-

FLC

(EQ. 12)

2. Calculate C1 such that FZ1 is placed at a fraction of the FLC,

at 0.1 to 0.75 of FLC (to adjust, change the 0.5 factor to

desired number). The higher the quality factor of the output

filter and/or the higher the ratio FCE/FLC, the lower the FZ1

frequency (to maximize phase boost at FLC).

-----------------------1-----------------------

2Ï â R2 â 0.5 â FLC

(EQ. 13)

3. Calculate C2 such that FP1 is placed at FCE.

C2 = -2---Ï-----â---R-----2----â---C-C----1-1---â---F----C----E-----â-----1-

(EQ. 14)

4. Calculate R3 such that FZ2 is placed at FLC. Calculate C3

such that FP2 is placed below FSW (typically, 0.5 to 1.0

times FSW). FSW represents the regulatorâs switching

frequency. Change the numerical factor to reflect desired

placement of this pole. Placement of FP2 lower in frequency

helps reduce the gain of the compensation network at high

frequency, in turn reducing the HF ripple component at the

COMP pin and minimizing resultant duty cycle jitter.

FN6288.5

October 7, 2008

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