ISL6524_14 Datasheet, PDF(8/16 Page) Intersil Corporation – VRM8.5 PWM and Triple Linear Power System Controller

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ISL6524_14 Datasheet, PDF (8/16 Pages) Intersil Corporation – VRM8.5 PWM and Triple Linear Power System Controller

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10V

3.0V

ATX 12V

ATX 5V

SS24

VTTPG

SS13

PGOOD

ATX 3.3V

VOUT4 (1.8V)

VOUT1 (1.65V)

VOUT3 (1.5V)

VOUT2 (1.2V)

T0 T1

T2 T3 T4 T5

TIME

FIGURE 6. SOFT-START INTERVAL

The T2 to T3 time interval is dependent upon the value of

CSS13. The same capacitor is also responsible for the ramp-

up time of the OUT1 and OUT3 voltages. If selecting a

different capacitor then recommended in the circuit application

literature, consider the effects the different value will have on

the ramp-up time and inrush currents of the OUT1 and OUT3

outputs.

Fault Protection

All four outputs are monitored and protected against extreme

overload. The chipâs response to an output overload is

selective, depending on the faulting output.

An overvoltage on VOUT1 output (VSEN1) disables outputs

1, 2, and 3, and latches the IC off. An undervoltage on

VOUT4 output latches the IC off. A single overcurrent event

on output 1, or an undervoltage event on output 2 or 3,

increments the respective fault counters and triggers a

shutdown of outputs 1, 2, and 3, followed by a soft-start re-

start. After three consecutive fault events on either counter,

the chip is latched off. Removal of bias power resets both the

fault latch and the counters. Both counters are also reset by

a successful start-up of all the outputs.

Figure 6 shows a simplified schematic of the fault logic. The

overcurrent latches are set dependent upon the states of the

overcurrent (OC1), output 2 and 3 undervoltage (UV2, UV3)

and the soft-start signals (SS13, SS24). Window

comparators monitor the SS pins and indicate when the

respective CSS pins are fully charged to above 4.0V (UP

signals). An undervoltage on either linear output (VSEN2,

VSEN3, or VSEN4) is ignored until the respective UP signal

goes high. This allows VOUT3 and VOUT4 to increase

without fault at start-up. Following an overcurrent event

(OC1, UV2, or UV3 event), bringing the SS24 pin below 0.8V

resets the overcurrent latch and generates a soft-started

ramp-up of the outputs 1, 2, and 3.

SS13UP

UV3

OC1

SS13

0.8V

SS24

UV4

LATCH

COUNTER

INHIBIT1,2,3

SSDOWN

SS24UP

POR

FAULT

LATCH

FAULT

COUNTER

UV2

LATCH

FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC

OUT1 Overvoltage Protection

The overvoltage circuit provides protection during the initial

application of power. For voltages on the VCC pin below the

power-on reset level (and above ~4V), the output level is

monitored for voltages above 1.3V. Should VSEN1 exceed

this level, the lower MOSFET, Q2, is driven on.

Overcurrent Protection

All outputs are protected against excessive overcurrents.

The PWM controller uses the upper MOSFETâs on-

resistance, rDS(ON) to monitor the current for protection

against a shorted output. All linear regulators monitor their

respective VSEN pins for undervoltage to protect against

excessive currents.

Figure 8 illustrates the overcurrent protection with an overload

on OUT1. The overload is applied at T0 and the current

increases through the inductor (LOUT1). At time T1, the OC1

comparator trips when the voltage across Q1 (iD â¢ rDS(ON))

exceeds the level programmed by ROCSET. This inhibits

outputs 1, 2, and 3, discharges the soft-start capacitor CSS24

with 28mA current sink, and increments the counter. Soft-start

capacitor CSS13 is quickly discharged. CSS13 starts ramping

up at T2 and initiates a new soft-start cycle. With OUT2 still

overloaded, the inductor current increases to trip the

overcurrent comparator. Again, this inhibits the outputs, but

the CSS24 soft-start voltage continues increasing to above

FN9015.3

April 18, 2005

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