ISL6524_14 Datasheet, PDF (13/16 Pages) Intersil Corporation – VRM8.5 PWM and Triple Linear Power System Controller

current value to the post-transient current level. During this
interval the difference between the inductor current and the
transient current level must be supplied by the output
capacitor(s). Minimizing the response time can minimize
the output capacitance required.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
t_RISE = -_VL---^O-_I--_N---^×--–---^I-_V-^T---^R-_O---^A-_U---^N-_T--
t_FALL
=
L_----O------×_----I_{--T----R----A----N--}
V_OUT
where: I_TRAN is the transient load current step, t_RISE is the
response time to the application of load, and t_FALL is the
response time to the removal of load. Be sure to check both
of these equations at the minimum and maximum output
levels for the worst case response time.
Input Capacitor Selection
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and
current ratings above the maximum input voltage and largest
RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25 times greater than the maximum
input voltage. The maximum RMS current rating requirement
for the input capacitors of a buck regulator is approximately
1/2 of the DC output load current. Worst-case RMS current
draw in a circuit employing the ISL6524 amounts to the
largest RMS current draw of the switching regulator.
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitance
for the high frequency decoupling and bulk capacitors to
supply the RMS current. Small ceramic capacitors can be
placed very close to the upper MOSFET to suppress the
voltage induced in the parasitic circuit impedances.
For a through-hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo
MV-GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.
MOSFET Selection/Considerations
The ISL6524 requires 5 external transistors. Two N-channel
MOSFETs are employed by the PWM converter. The GTL,
AGP, and memory linear controllers can each drive a
MOSFET or a NPN bipolar as a pass transistor. All these
transistors should be selected based upon r_DS(ON), current
gain, saturation voltages, gate supply requirements, and
thermal management considerations.
PWM MOSFET Selection and Considerations
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the dominant
design factors. The power dissipation includes two main loss
components: conduction losses and switching losses. These
losses are distributed between the upper and lower MOSFET
according to the duty factor. The conduction losses are the
main component of power dissipation for the lower MOSFETs.
Only the upper MOSFET has significant switching losses, since
the lower device turns on and off into near zero voltage.
The equations presented assume linear voltage-current
transitions and do not model power losses due to the lower
MOSFET’s body diode or the output capacitances associated
with either MOSFET. The gate charge losses are dissipated
by the controller IC (ISL6524) and do not contribute to the
MOSFETs’ heat rise. Ensure that both MOSFETs are within
their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal resistance specifications. A separate
heatsink may be necessary depending upon MOSFET power,
package type, ambient temperature and air flow.
P_UPPER
=
I_--O-----²_----×_-----r_{--D----S----(--O-----N----)---}×_-----V_{----O-----U----T-- + -}I_-O------×_-----V_{----I--N-----}×_-----t_{--S----W------}×_-----F_----S--
V_IN
2
P_LOWER
=
I_--O-----²_----×_-----r_{--D----S----(--O-----N----)---}×_-----(_---V_{----I--N-----–----}V_{-----O----U----T----})
V_IN
The r_DS(ON) is different for the two equations above even if
the same device is used for both. This is because the gate
drive applied to the upper MOSFET is different than the
lower MOSFET. Figure 13 shows the gate drive where the
upper MOSFET’s gate-to-source voltage is approximately
V_CC less the input supply. For +5V main power and +12VDC
for the bias, the approximate gate-to-source voltage of Q1 is
7V. The lower gate drive voltage is 12V. A logic-level
MOSFET is a good choice for Q1 and a logic-level MOSFET
can be used for Q2 if its absolute gate-to-source voltage rating
exceeds the maximum voltage applied to V_CC.
13
FN9015.3
April 18, 2005