ISL6524_14 Datasheet, PDF (14/16 Pages) Intersil Corporation – VRM8.5 PWM and Triple Linear Power System Controller

+12V
VCC
ISL6524
UGATE
PHASE
-
LGATE
+
PGND
GND
+5V OR LESS
Q1
NOTE:
V_GS ≈ V_CC -5V
Q2
CR1
NOTE:
V_GS ≈ V_CC
FIGURE 13. UPPER GATE DRIVE - DIRECT V_CC DRIVE
Rectifier CR1 is a clamp that catches the negative inductor
swing during the dead time between the turn off of the lower
MOSFET and the turn on of the upper MOSFET. For best
results, the diode must be a surface-mount Schottky type to
prevent the parasitic MOSFET body diode from conducting. It
is acceptable to omit the diode and let the body diode of the
lower MOSFET clamp the negative inductor swing, but one
must ensure the PHASE node negative voltage swing does
not exceed -3V to -5V peak. The diode's rated reverse
breakdown voltage must be equal or greater to 1.5 times the
maximum input voltage.
Linear Controllers Transistor Selection
The ISL6524 linear controllers are compatible with both NPN
bipolar as well as N-channel MOSFET transistors. The main
criteria for selection of pass transistors for the linear
regulators is package selection for efficient removal of heat.
The power dissipated in a linear regulator is
P_LINEAR = I_O × (V_IN – V_OUT)
Select a package and heatsink that maintains the junction
temperature below the maximum desired temperature with
the maximum expected ambient temperature.
When selecting bipolar NPN transistors for use with the
linear controllers, insure the current gain at the given
operating V_CE is sufficiently large to provide the desired
output load current when the base is fed with the minimum
driver output current.
In order to ensure the strict timing/level requirement of
OUT4, an NPN transistor is recommended for use as a pass
element on this output (Q5). A low gate threshold NMOS
could be used, but meeting the requirements would then
depend on the VCC bias being sufficiently high to allow
control of the MOSFET.
14
FN9015.3
April 18, 2005