ISL6296A Datasheet, PDF (8/20 Pages) Intersil Corporation – FlexiHash For Battery Authentication

ISL6296A
secrets chosen, and finally compares the result with the
authentication code read from the device. If the codes do not
match up, the device is a fake device and the host may shut
itself down. The flow chart in Figure 6 summarizes the
process that the host needs to execute.
It is recommended that device authentication be done once
in a while to maximize its effectiveness. Before a new
challenge code can be accepted by the device, the SESL
register must be re-written again to ensure that the original
seeds are re-loaded from the OTP ROM into the hash
engine prior to performing the next authentication code
calculation. Failure to follow the sequence will result is a bus
error, causing the sBER flag to be set in the STAT register.
64-BIT SECRET
32-BIT HASH FUNCTION
32-BIT HASH SEED
32-BIT PSEUDO-RANDOM
CHALLENGE WORD FROM HOST
FLEXIHASH
ENGINE
START
WAKE UP ISL6296A USING A
REGULAR BREAK SIGNAL
SELECT HASH FUNCTION AND SEED
BY WRITING TO SESL REGISTER
SEND A 32-BIT RANDOM
CHALLENGE TO CHLG REGISTER
READ THE AUTHENTICATION
RESULT FROM AUTH REGISTER,
AFTER WAITING FOR 1 BT_D
CALCULATE THE EXPECTED
AUTHENTICATION RESULT
BASED ON THE SAME SECRETS
NO
THE TWO RESULTS MATCH?
8-BIT AUTHENTICATION
CODE
FIGURE 5. AUTHENTICATION PROCESS FLOW DIAGRAM
SET-UP FOR DEVICE AUTHENTICATION SUPPORT
To configure the host and the ISL6296A to support device
authentication function, the pack manufacturer will need to
select at least 2 sets of 32-bit secret codes. For greater
security, a third set of 32-bit secret may be used. The
FlexiHash engine requires two sets of 32-bit secrets for use
in its hash calculation; the first set to define its hash function,
and the second set to initialize its seed for hash calculation.
These two sets can be selected from the same secret
location. The chosen secret codes are to be kept by the pack
manufacturer and maintained at utmost confidentiality.
After the secrets have been determined, they are written into
the device’s OTP ROM. After verification that the codes have
been written in correctly, the relevant secrets lock-out bits at
ROM address location 0-00 should be set. Once set, the
lock-out bits can no longer be cleared. Thereafter, read/write
access to the secret information will no longer be possible,
and the secret codes are made available only to the
FlexiHash engine for generation of authentication code
based on a challenge code input from the host.
On the host side, the same secret codes will need to be kept,
and the same FlexiHash engine will have to be implemented in
firmware. Refer to Application Note AN1166 for detailed
information of firmware implementation. It is important that the
secret codes be stored scrambled in the host’s non-volatile
memory so that the secret information cannot be easily
revealed by monitoring signal transfer on the host PCB.
YES
SHUT DOWN
THE SYSTEM
END
FIGURE 6. FLOW CHART FOR AUTHENTICATION PROCESS
THE HASH ENGINE
The hash engine consists of 4 separate programmable 8-bit
CRC calculators. Two sets of 32-bit secret codes are used
by the hash engine for authentication code generation. The
first set is used to define the CRC polynomial as well as the
input selection for each of the CRC calculators. The second
is used as initial seeds for the CRC calculations. Outputs of
the 4 CRC calculators are logically combined to produce the
8-Bit output of the overall FlexiHash engine. The Block
Diagram of the FlexiHash engine is illustrated in Figure 7.
More detailed descriptions on the hash engine can be found
in Application Note AN1166.
8
FN6567.3
April 15, 2010