ISL6296A Datasheet, PDF (6/20 Pages) Intersil Corporation – FlexiHash For Battery Authentication

ISL6296A
Theory of Operation
The ISL6296A contains all circuitry required to support battery
pack authentication based on a challenge-response scheme.
It provides a 16-Byte One-Time Programmable Read-Only
Memory (OTPROM) space for the storage of up to 96 bits of
secret for the authentication and other user information. A
32-bit CRC-based hash engine (FlexiHash) calculates the
authentication result immediately after receiving a 32-bit
random challenge code. The communication between the
ISL6296A and the host is implemented through the XSD
single-wire communication bus.
Major functions within the ISL6296A include the following, as
shown in Figure 3:
• Power-on reset (POR) and a 2.5V regulator to power all
internal logic circuits.
• 16x8-Bit (16-Byte) OTP ROM as shown in Table 8. The
first part (two bytes) contains the device default
configuration (DCFG) information (such as the device
address and the XSD communication speed) and the
default trimming (DTRM) information (such as the internal
oscillator frequency trimming). The second part contains
two groups (12-Byte) of memory that can be
independently locked out for the storage of up to three
sets of secret codes. The last part provides two additional
bytes of space for general-purpose information.
• Control functions, including master control (MSCR) and
status (STAT) registers (as shown in Table 9), interrupt
generation, and the test-related interface.
• FlexiHash engine that includes the 32-Bit CRC-based
hash engine, secret selection register, challenge code
register and the authentication result register. Table 10
shows all the registers.
• XSD communication bus Interface. The XSD device
address and the communication speed are configured in
the DCFG address in the OTPROM, as given in Table 8.
• Time Base Reference.
The following explains in detail the operation of the
ISL6296A.
Power-On Reset (POR)
The ISL6296A powers up in Sleep mode. It remains in Sleep
mode until a power-on ‘break’ command is received from the
host through the XSD bus. The initial power-on ‘break’ can
be of any pulse width, as long as it is wider than the XSD
input de-glitch time (20µs). Once the ‘break’ command is
received, the internal regulator is powered up. About 20µs
after the falling edge of the power-on ‘break’, an internal
POR circuit releases the reset to the digital block, and a
POR sequence is started. During the POR sequence, the
ISL6296A initializes itself by loading the default device
configuration information from pre-assigned locations within
the OTP ROM memory. After initialization, a ‘break’
command is returned to the host to indicate that the
ISL6296A is ready and waiting for a bus transaction from the
host.
HOST BREAK
DEVICE BREAK
XSD BUS
WAVEFORM
60µs
TYP
1.391
BT _D
FIGURE 4A. WHEN THE HOST POWER-ON BREAK IS WIDER
THAN 60µs
HOST BREAK
DEVICE BREAK
XSD BUS
WAVEFORM
FIGURE 4B. WHEN THE HOST POWER-ON BREAK IS
NARROWER THAN 60µs
FIGURE 4. POWER-ON BREAK SIGNAL TO WAKE-UP THE
ISL6296A FROM SLEEP MODE
Note that the ISL6296A will initiate the power-on sequence
without waiting for the power-on ‘break’ signal to return to the
high state. If the host sends an initial ‘break’ pulse wider than
60µs, the device-ready ‘break’ returned by the ISL6296A will
likely be merged with the pulse sent by the host and,
therefore, may not be detectable. Figure 4 illustrates the
waveforms during the Power-on Reset. Figure 4A represents
the case when the power-on ‘break’ rising edge occurs after
the device starts sending the ‘break’. Figure 4B represents the
case when the power-on ‘break’ finishes before the device
sends its ‘break’. The device break signal is always 1.391
times of the device bit-time (BT, see “XSD Host Bus Interface”
on page 10 for more details). Either case in Figure 4 will
wake-up the device successfully if the device is in the sleep
mode.
Note that It is important to keep in mind that a narrow ‘break’
signal will be taken as a normal bit signal and cause errors if
the device is not in the sleep mode. For this reason, the
narrow power-on ‘break’ signal should be used only if the
user has to see the returned ‘break’ signal.
Auto-Sleep
While the ISL6296A is powered up and there is no bus
activity for more than about 1s, the device will automatically
return to Sleep mode. Sleep mode can be entered
independent of whether the XSD bus is held high or low.
While the ISL6296A is in Sleep mode, it is recommended
that the XSD bus be held low to eliminate current drain
through the XSD-pin internal pull-down current.
6
FN6567.3
April 15, 2010