ISL6271A Datasheet, PDF (8/16 Pages) Intersil Corporation – Integrated XScale Regulator

ISL6271A
Operational Description
Initialization
Upon application of input power to the ISL6271A, the power
good signal (PGOOD) will switch from low to high after four
conditions are met - (1) VCC exceeds the power on reset
“rising threshold”, (2) the EN pin is high and (3) the LDO
input voltage (LVCC) is greater than 1.6V, (4) All three
outputs are in regulation. Figure 16 illustrates this start-up
sequence. The outputs are powered on under a soft-start
regime with the core output voltage defaulting to 1.3V
(unless under VID control) and the LDOs at their fixed output
levels. Once the outputs are in regulation, the ISL6271A will
respond to a voltage change command via the I²C bus.
When under VID control (VIDEN = HI), the Vout will rise to a
value set by VID pins. The slew rate is always fixed by the
soft-start capacitor.
Core Regulator Output
The ISL6271A core regulator is a synchronous buck
regulator that employs an Intersil proprietary switch-mode
topology known as Synthetic Ripple Regulation (SRR). The
SRR architecture is a derivative of the conventional
hysteretic-mode regulator without the inherent noise
sensitivities and dependence on output capacitance ESR.
The topology achieves excellent transient response and high
efficiency over the entire operating load range. Output
voltage ripple is typically under 5mV in Continuous
Conduction Mode (CCM) and under 10mV in DCM (diode
emulation). The output core voltage is derived from the main
battery pack (typically a single cell Li-ion battery) and is
programmable in 50mV steps between 0.85 and 1.6V. The
output regulator set-point is controlled by an on-chip DAC
which receives its input either from the I²C bus or the VID
input pins (VID0-VID3). Table 1 identifies the VID code
states and corresponding output voltage. To minimize core
voltage over-shoot and under-shoot between code states,
the ISL6271A implements programmable, voltage slew rate
control via the I²C bus. The slew rate is a function of the data
in the slew rate control register and also the soft-start
capacitor; the slew rates in Table 2 assume a soft-start
capacitor value of 10nF. Once the regulator has initialized,
the IC can be placed in a low quiescent state by pulling low
the EN pin. The regulator ‘remembers’ the last programmed
voltage level and slew rate after each subsequent EN cycle,
and return to the previous set-point once EN is brought high.
MSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
TABLE 1. VOLTAGE-SET COMMAND BITS
I²C DATA BYTE OR VID PINS
LSB NOMINAL
D3 D2 D1 D0 OUTPUT
XXX0 0 0 0
0.850
XXX0 0 0 1
0.900
XXX0 0 1 0
0.950
XXX0 0 1 1
1.000
XXX0 1 0 0
1.050
XXX0 1 0 1
1.100
XXX0 1 1 0
1.150
XXX0 1 1 1
1.200
XXX1 0 0 0
1.250
XXX1 0 0 1
1.300
XXX1 0 1 0
1.350
XXX1 0 1 1
1.400
XXX1 1 0 0
1.450
XXX1 1 0 1
1.500
XXX1 1 1 0
1.550
XXX1 1 1 1
1.600
VCC
SYSTEM TIMING
2.8V TYP.
RISING POR
THRESHOLD
2.6V TYP.
FALLING POR
THRESHOLD
BFLT#
EN
I2C, SCL
Data transferred to the
reference DAC on the
rising edge of SCL
during the ACK bit
SOFT-START
SLEW RATE
VOUT
1.3V
1.0V
I²C PROGRAMMABLE
SLEW RATE
VPLL, VSRAM
PGOOD
FIGURE 16. SYSTEM TIMIMG DIAGRAM
8
FN9171.1