ISL6271A Datasheet, PDF (1/16 Pages) Intersil Corporation – Integrated XScale Regulator

®
Data Sheet
October 8, 2004
ISL6271A
FN9171.1
Integrated XScale Regulator
The ISL6271A is a versatile power management IC (PMIC)
designed for the Xscale type of processors. The device
integrates three regulators, two fault indicators and an I²C
bus for communication with a host microprocessor. Two of
the three regulators function as low power, low drop out
regulators, designed to power SRAM and phase-lock loop
circuitry internal to the Xscale processor. The third regulator
uses a proprietary switch-mode topology to power the
processor core and facilitate Dynamic Voltage Management
(DVM), as defined by Intel.
Since power dissipation inside a microprocessor is
proportional to the square of the core voltage, Intel XScale
processors implement DVM as a means to more efficiently
utilize battery capacity. To support this power saving
architecture, the ISL6271A integrates an I²C bus for
communication with the host processor. The processor, acting
as the bus master, transmits a “voltage level” and “voltage
slew rate” to the ISL6271A appropriate to the processing
requirements; higher core voltages support higher operating
frequencies and code execution. The bus is fully compliant
with the Phillips® I²C protocol and supports both standard
and fast data transmission modes. Alternatively, the output of
the core regulator can be programmed in 50mV increments
from 0.85V to 1.6V using the input Voltage ID (VID) pins. All
three regulators share a common enable pin and are
protected against overcurrent, over temperature and
undervoltage conditions. When disabled via the enable pin,
the ISL6271A enters a low power state that can be used to
conserve battery life while maintaining the last programmed
VID code and slew rate. An integrated soft-start circuit
transitions the ISL6271A output voltages to their default
values at a rate determined by an external soft-start capacitor.
Pinout
ISL6271A (4x4 QFN) TOP VIEW
20 19 18 17 16
VCC 1
15 LVCC
VIDEN 2
14 VPLL
SCL/VID0 3
13 VSRAM
SDA/VID1 4
VID2 5
12 FB
11 VOUT
6 7 8 9 10
Features
• Three Voltage Regulators (1 Buck, 2 LDOs)
• High-Efficiency, fully-Integrated synchronous buck
regulator with DVM
• 800mA DC output current for the buck regulator
• Proprietary ‘Synthetic Ripple’ Control Topology
• Greater than 1MHz Switching Frequency
• Diode emulation for light load efficiency
• I²C Interface Module for DVM from 0.85V to 1.6V
• Optional fixed 4-bit VID-control in lieu of DVM
• Small Output Inductor and Capacitor
• Battery Fault signal
• Input Supply Voltage Range: 2.76V-5.5V
• 4x4 mm QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-free Available (RoHS Compliant)
Applications
• PDA
• Cell Phone
• Tablet Devices
• Embedded Processors
Related Literature
• Technical Brief TB379 “Thermal Characterization of
Packaged Semiconductor Devices”
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages“
• Application Note AN1139 “Setup Instruction for the
ISL6271 Evaluation Kit”
Ordering Information
PART NUMBER*
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
ISL6271ACR
-25 to 85 20 Ld 4x4 QFN L20.4x4
ISL6271ACRZ (Note)
-25 to 85
20 Ld 4x4 QFN L20.4x4
(Pb-free)
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both
SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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