ISL6271A Datasheet, PDF (14/16 Pages) Intersil Corporation – Integrated XScale Regulator

ISL6271A
Measured Core Voltage Conversion Efficiency
The actual efficiency of the ISL6271A switching regulator is
illustrated in Figure 3 from 10mA to 800mA. The curves were
taken at room temperature using the ISL6271A evaluation
board. The output inductor used is an ultralow profile,
drumcore device with a DCR of 100mΩ.
10mV RIPPLE
IN DCM
CCM
RIPPLE
TOTAL POWER SOLUTION
(INTEL XScale PROCESSOR)
VCC_LCD
VCC_MEM
EL7536
3.3V
OUTPUT
REGULATOR
EN
BATT
TO
3V LDO
VCC_IO
VCC_BB
VCC_USB
VCC_BATT
MOS
SWITCH
INTEL
Xscale
µP
VCC_USIM
nVDD_FLT
nBatt_FLT
VCC_CORE
VCC_SRAM
VCC_PLL
I²C_SDA
I²C_SCL
SINGLE
CELL
ISL6271A ^LI-Ion
PMIC
EN
PWR_EN
SYS_EN
FIGURE 24. DCM TO CCM MODE TRANSITION
Thermal Management
Although the ISL6271A is characteristically a low heat
generator, it will generate some heat as a result of the
inefficiencies in power conversion. The worst-case internal
power dissipation should be less than 250mW, translating
into a 11°C rise in junction temperature above ambient. If the
temperature of the chip does exceed 150° ±10°C as a result
of a high ambient temperature, the controller will disable the
outputs until the temperature decreases by 45°C.
Powering Intel XScale Processors
Intel identifies ten power domains required for powering
XScale processors. Of these ten power domains or voltages,
many may be strapped together as in Figure 25 and supplied
by a single regulator. These voltages however must be
applied systematically to the processor and two pins,
SYS_EN and PWR_EN facilitate this power sequence. The
PWR_EN pin is dedicated to enabling the CORE, PLL and
SRAM power domains and should be connected to the
ISL6271A enable pin. The SYS_EN pin is responsible for
enabling the system regulator. Figure 25 illustrates one
possible configuration using the Intersil EL7536 to power five
of the 10 domains.
NOTE: Intel warns that an improper power sequence can damage
the processor. Refer to the appropriate Intel applications material to
ensure proper voltage sequencing.
FIGURE 25. XSCALE POWER DOMAINS
Design Notes
Refer to Table 3, "RECOMMENDED KEY COMPONENT
VALUES FOR CORE REGULATOR".
1. Do not leave pins VID2(5) or pin VID3(6) floating when
using the I²C bus. Tie these pins to GND (16).
2. Make sure that load current on VOUT returns to the pin 7
(PGND). Pin 16 (GND) functions as a quiet return for the
LVCC loads. Tie Pin 16 to Pin 7 at a single point as in
Figure 19.
3. Select the output capacitor for VSRAM and VPLL as
follows: 2.2µF<C8, C5<4.7µF, X5R.
4. BFLT# is internally pulled up to BBAT. Do not pullup to
any other external voltage.
5. The I²C pull-up resistors will affect standby leakage
power. A typical value to accommodate the I²C bus slew
rate requirements in “Standard Mode” is 5K.
6. Set the soft-start capacitor to 10nF to implement a
1mV/µs slew rate of the output voltage at startup. For
max slew rate, use 6.8nF soft-start capacitor.
7. Tie PGOOD to the XScale nVDD_fault pin.
8. Tie the BFLT# pin to the XScale nBatt_fault pin. The
BFLT# pin is pulled up internally to BBAT. A valid BFLT#
state under all conditions can be achieve by connecting
BBAT to the system BACK-UP battery. Otherwise,
consider the system start-up/shut-down voltage timing to
determine what system voltage that BBAT can be tied to
that will ensure the correct BFLT# operation. Current
drain on BBAT is much less than 1µA.
9. It is a good design practice to isolate PVCC from VCC
with a low pass filter (LPF) made up of a 10Ω resistor and
0.1µF ceramic capacitor. Ensure that VCC is kept within
0.3V of PVCC to avoid turning on internal protection
diodes.
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FN9171.1