ISL6271A Datasheet, PDF (11/16 Pages) Intersil Corporation – Integrated XScale Regulator

ISL6271A
I²C SEND BYTE PROTOCOL
S 0 00 1 10 0 00 X
START _A6 A5 A4 A3 A2 A1 A0 _{W A}
SLAVE ADDRESS
SLEW ^VOLTAGE
SET
X D5 D4 D3 D2 D1 D0 0 P
A STOP
COMMAND BYTE
I²C RECEIVE BYTE PROTCOL
S 0 0 0 1 1 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1 P
START A6 A5 A4 A3 A2 A1 A0 W A
A STOP
SLAVE ADDRESS
DATA BYTE
FIGURE 18. INTERFACE BIT DEFINITION AND PROTOCOL
VID and Slew Rate Program Register
In a typical XScale configuration, the processor’s “Power
Manager” will issue the voltage and slew rate commands to
the ISL6271A over its PWR_ I²C bus after the ISL6271A
acknowledges its address. The data byte is composed of two
pieces of ‘set’ information: The prescribed voltage level
embedded in bits D0-D3, and the prescribed transition slew
rate (from the previous voltage to the target voltage)
embedded in bits D4-D5. Each set of bits is transmitted MSB
first. This protocol is depicted in Figure 18.
Application Guidelines
Every effort should be made to place the ISL6271A as close
as possible to the processor, with the orientation favoring the
shortest voltage routing. The regulator input capacitors
should be located close to their respective input pins.
All output capacitors should be kept close to their respective
output pins with the ground pins connected immediately to
the ground plane. Care should be taken to avoid routing
sensitive, high impedance signals near the PHASE pin on
the controller, and the attendant PCB traces.
To minimize switching noise, it is important to keep the loop
area associated with the phase node and output filter as
short as possible. It is also important that the input voltage
decoupling capacitor C7 be located as close to the PVCC
pin as possible and that it has a low impedance return path
to the PGND pin. In general a good approach to layout is to
consider how switching current flows in a circuit, and to
minimize the loop area associated with this current. In the
case of the switching regulator, current flows from C7
through the internal upper P-MOSFET, to the load through
the output filter and back to the PGND pin. To maximize the
effectiveness of any decoupling capacitor, minimize the
parasitic inductance between the capacitor and the circuit it
is decoupling. Notice that Figure 19 illustrates the SIGNAL
ground with RED highlighting. All components associated
with these terminals should be tied together first. Be sure to
make only one connection between this net and the PGND
pin to avoid ground loops and noise injection points into
sensitive analog circuitry.
BBAT ≤ VCC
COIN CELL
BACK-UP
Li-ion
4.2V
TO
2.60V
R7, 10Ω
C3
0.1µF
C7
10µF
1.8V
C2
OR 2.5V _2.2µF
C4
10nF
X7R
ISL6271A
BBAT
PVCC
SCL/VID0
SDA/VID1
VCC
PGOOD
BFLT#
EN
LVCC
VSRAM
SOFT
VIDEN
VID2
VID3
GND
VPLL
FB
VOUT
PHASE
PGND
Single point connection
between PGND and GND pins
5kΩ 5kΩ 5kΩ
C8
2.2µF
X5R
Rcomp, 50K
C5
2.2µF
X5R
XScale µP
PWR_I2C
FAULT
REG. EN
VCC_SRAM
VCC_PLL
VCC_CORE
L1
4.7µH
C6
10µF
X5R
Power ground. Minimize the loop area associated
with L1, C6 and the PHASE and PGND pins.
FIGURE 19. TYPICAL APPLICATION CIRCUIT
11
FN9171.1