ISL5416_04 Datasheet, PDF (8/71 Pages) Intersil Corporation – Four-Channel Wideband Programmable DownConverter

CLKC
CLKX
R1
CLKC
CLKX
ISL5416
R2
R3 R4
R1 R2
R3 R4
ENIX
XIN(16:0)
CLK/CLK
BUS REVERSE FLOAT/FIX
OBIN
SLOT#
R1
R2
R3
R4
R
R
E
G
R
E
G
R
E
G
R
F
E (16:0)
M
R
G
M
T
M
^
^
^
^
U
(0:16) _X
A
P
MUX
DR
ME
UG
X_^
INTERPOLATE
MANTISSA
EXPONENT
PROCESSING
ENABLE
TO CHANNELS
AND RANGE
CONTROL
CLKX/CLKC
CLKX
CLKC
MUX
DIN (ONLY)
TO SERIAL
FREQUENCY
OFFSET
CLK
NOTE: To simplify the board routing, each of the four input data busses can be reversed, MSB for LSB (see IWA = 0*00h, bit 4)
FIGURE 1. INPUT SECTION
SYNCInX Use
SYNCInX main purpose is as a processing start-up signal
after a reset to align the start of processing of multiple
channels or chips. This assures that the carrier phases have
a known relationship and that the output timing aligns for
multiplexing outputs. It can also be used after start-up as a
system timing synchronization signal. Two SYNCInX signals
are provided so that one can be used as a regularly
occurring signal (such as at time slot boundaries) and one
as an infrequent signal (such as at start up or at 1 pps). If
more than one air interface standard is processing in one
part, one SYNCInX signal could be used for the slot timing
for each standard.
Register updates from a processor write are synchronized to
the clock, so that the register updates in multiple channels of
the same part are time aligned. However, when
synchronizing multiple parts the processor will need
knowledge of the SYNCInX timing so that enabling the
SYNCInX in multiple parts occurs between SYNCInX pulses.
Alternatively, SYNCIn1 could be used as a regularly
occurring SYNCI signal and SYNCIn2 could be a gated
version. The channel processing control register might only
be updated on SYNCIn2 and the other SYNCI functions
would respond to SYNCIn1.
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