ISL5416_04 Datasheet, PDF (39/71 Pages) Intersil Corporation – Four-Channel Wideband Programmable DownConverter

ISL5416
TABLE 29. HIGH, LOW BYTE DATA TYPE CODES (AFTER
ROUNDING IN THE CHANNEL)
CODE
CHANNEL 0, CHANNEL CHANNEL 2, CHANNEL
1 MUXES
3 MUXES
0000 CH 0 I(23:16)
CH 2 I(23:16)
0001 CH 0 I(15:8)
CH 2 I(15:8)
0010 CH 0 I(7:0)
CH 2 I(7:0)
0011 CH 0 Q(23:16)
CH 2 Q(23:16)
0100 CH 0 Q(15:8)
CH 2 Q(15:8)
0101 CH 0 Q(7:0)
CH 2 Q(7:0)
0110 CH 0 AGC(15:8)
CH 2 AGC(15:8)
0111 CH 0 AGC(7:0)
CH 2 AGC(7:0)
1000 CH 1 I(23:16)
CH 3 I(23:16)
1001 CH 1 I(15:8)
CH 3 I(15:8)
1010 CH 1 I(7:0)
CH 3 I(7:0)
1011 CH 1 Q(23:16)
CH 3 Q(23:16)
1100 CH 1 Q(15:8)
CH 3 Q(15:8)
1101 CH 1 Q(7:0)
CH 3 Q(7:0)
1110 CH 1 AGC(15:8)
CH 3 AGC(15:8)
1111 CH 1 AGC(7:0)
CH 3 AGC(7:0)
Serial Output:
When bit 31 of GWA = 0000h is set, the DOUT bus is used
for serial outputs.
Four bits are allocated to each channel as follows:
TABLE 30. SERIAL OUTPUT BITS ALLOCATION
CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3
SCLKX DOUT0
DOUT4
DOUT8
DOUT12
SSYNCX DOUT1
DOUT5
DOUT9
DOUT13
SD1X
DOUT2
DOUT6
DOUT10
DOUT14
SD2X
DOUT3
DOUT7
DOUT11
DOUT15
A common serial clock generator is used for all four outputs,
so the four SCLKs are synchronous. Four separate outputs
are provided to simplify PWB routing. Each SCLK output can
be separately enabled, so that unused clock outputs can be
turned off.
Serial outputs are always MSB first.
Addresses 0106h to 0108h control the serial output from
channel 0.
Addresses 0206h to 0208h control the serial output from
channel 1.
Addresses 0406h to 0408h control the serial output from
channel 2.
Addresses 0806h to 0808h control the serial output from
channel 3.
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