ISL5416_04 Datasheet, PDF (22/71 Pages) Intersil Corporation – Four-Channel Wideband Programmable DownConverter

ISL5416
Data Output Formatter Section
Four 16-bit output data busses are provided on the ISL5416.
All of the busses share a common output clock, CLKO1,
which is derived from CLKC. CLKO2 signal is provided for
easier board routing or for the differential outputs. Each bus
has an output SYNC which is typically used as a frame sync.
Each bus can be divided into two 8-bit busses if desired.
When a new data sample is available from a channel, it
starts a time slot counter that sequences through up to 8
output time slots. The data type for each time slot is
programmable as well as the FSYNCx assertion. The data
from more than one channel can be multiplexed through the
same output bus if channels are synchronized. The data
from channels 0 and 1 and from channels 2 and 3 can be
multiplexed directly. Multiplexing channels 0 and 1 with 2 and
3 is done by ORing multiplexer outputs together. See figures
10 and 11. This means that related channels (such as
diversity channels) should be grouped into channels 0 and 1,
or into channels 2 and 3 for ease of data routing.
The data type, SYNC assertion, and bus routing are
programmed in registers 0*01h through 0*04h. Two of the
eight time slots are programmed in each location.
The I/Q data from each channel is rounded to 4, 6, 8, 12, 16,
20 or 24 bits at the output of the channel. The AGC gain can
be rounded to 8, 12, or 16 bits. A 24-bit output is provided to
the output section for I and Q data and a 16-bit output is
provided for the AGC data. The data is MSB justified in the
output bus and the LSBs below the programmed number are
zeroed.
24 bits of I/Q data is available from the AGC if the
IHBF/HOIF is bypassed. I/Q are 16 bits if the IHBF/HOIF
section is enabled.
Serial outputs are available. See GWA = 0000h, IWA =
0*06h, 0*07h, and 0*08h.
I0
Q0
AGC0
I1
Q1
AGC1
(23:16)
(15:8)
(7:0)
(23:16)
(15:8)
(7:0)
(15:8)
(7:0)
(23:16)
(15:8)
(7:0)
(23:16)
(15:8)
(7:0)
(15:8)
(7:0)
(15:8)
I0
Q0
AGC0
I1
Q1
AGC1
(23:16)
(15:8)
(7:0)
(23:16)
(15:8)
(7:0)
(15:8)
(7:0)
(23:16)
(15:8)
(7:0)
(23:16)
(15:8)
(7:0)
(15:8)
(7:0)
01 AC UPPER
Channels
Output Byte
Outputs
FIGURE 9. MULTIPLEXING CHANNELS
(7:0)
22